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drivers: timer: litex_timer: Fix sys_clock_cycle_get functions

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e8e88dea incorrectly changed registers
used in `sys_clock_cycle_get(32|64)` functions.

This commit fixes that.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
This commit is contained in:
Michal Sieron 2022-05-06 13:12:13 +02:00 • committed by Carles Cufí
commit eff89c6b24
2 changed files with 25 additions and 19 deletions
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36
drivers/timer/litex_timer.c
View file

@ -13,20 +13,22 @@
#include <zephyr/spinlock.h> #include <zephyr/spinlock.h>
#include <zephyr/drivers/timer/system_timer.h> #include <zephyr/drivers/timer/system_timer.h>
#define TIMER_LOAD_ADDR DT_INST_REG_ADDR_BY_NAME(0, load) #define TIMER_LOAD_ADDR DT_INST_REG_ADDR_BY_NAME(0, load)
#define TIMER_RELOAD_ADDR DT_INST_REG_ADDR_BY_NAME(0, reload) #define TIMER_RELOAD_ADDR DT_INST_REG_ADDR_BY_NAME(0, reload)
#define TIMER_EN_ADDR DT_INST_REG_ADDR_BY_NAME(0, en) #define TIMER_EN_ADDR DT_INST_REG_ADDR_BY_NAME(0, en)
#define TIMER_UPDATE_VALUE_ADDR DT_INST_REG_ADDR_BY_NAME(0, update_value) #define TIMER_UPDATE_VALUE_ADDR DT_INST_REG_ADDR_BY_NAME(0, update_value)
#define TIMER_VALUE_ADDR DT_INST_REG_ADDR_BY_NAME(0, value) #define TIMER_VALUE_ADDR DT_INST_REG_ADDR_BY_NAME(0, value)
#define TIMER_EV_STATUS_ADDR DT_INST_REG_ADDR_BY_NAME(0, ev_status) #define TIMER_EV_STATUS_ADDR DT_INST_REG_ADDR_BY_NAME(0, ev_status)
#define TIMER_EV_PENDING_ADDR DT_INST_REG_ADDR_BY_NAME(0, ev_pending) #define TIMER_EV_PENDING_ADDR DT_INST_REG_ADDR_BY_NAME(0, ev_pending)
#define TIMER_EV_ENABLE_ADDR DT_INST_REG_ADDR_BY_NAME(0, ev_enable) #define TIMER_EV_ENABLE_ADDR DT_INST_REG_ADDR_BY_NAME(0, ev_enable)
#define TIMER_UPTIME_LATCH_ADDR DT_INST_REG_ADDR_BY_NAME(0, uptime_latch)
#define TIMER_UPTIME_CYCLES_ADDR DT_INST_REG_ADDR_BY_NAME(0, uptime_cycles)
#define TIMER_EV 0x1 #define TIMER_EV 0x1
#define TIMER_IRQ DT_INST_IRQN(0) #define TIMER_IRQ DT_INST_IRQN(0)
#define TIMER_DISABLE 0x0 #define TIMER_DISABLE 0x0
#define TIMER_ENABLE 0x1 #define TIMER_ENABLE 0x1
#define TIMER_UPDATE_VALUE 0x1 #define TIMER_UPTIME_LATCH 0x1
static void litex_timer_irq_handler(const void *device) static void litex_timer_irq_handler(const void *device)
{ {
@ -41,29 +43,29 @@ static void litex_timer_irq_handler(const void *device)
uint32_t sys_clock_cycle_get_32(void) uint32_t sys_clock_cycle_get_32(void)
{ {
static struct k_spinlock lock; static struct k_spinlock lock;
uint32_t timer_value; uint32_t uptime_cycles;
k_spinlock_key_t key = k_spin_lock(&lock); k_spinlock_key_t key = k_spin_lock(&lock);
litex_write8(TIMER_UPDATE_VALUE, TIMER_UPDATE_VALUE_ADDR); litex_write8(TIMER_UPTIME_LATCH, TIMER_UPTIME_LATCH_ADDR);
timer_value = (uint32_t)litex_read64(TIMER_VALUE_ADDR); uptime_cycles = (uint32_t)litex_read64(TIMER_UPTIME_CYCLES_ADDR);
k_spin_unlock(&lock, key); k_spin_unlock(&lock, key);
return timer_value; return uptime_cycles;
} }
uint64_t sys_clock_cycle_get_64(void) uint64_t sys_clock_cycle_get_64(void)
{ {
static struct k_spinlock lock; static struct k_spinlock lock;
uint64_t timer_value; uint64_t uptime_cycles;
k_spinlock_key_t key = k_spin_lock(&lock); k_spinlock_key_t key = k_spin_lock(&lock);
litex_write8(TIMER_UPDATE_VALUE, TIMER_UPDATE_VALUE_ADDR); litex_write8(TIMER_UPTIME_LATCH, TIMER_UPTIME_LATCH_ADDR);
timer_value = litex_read64(TIMER_VALUE_ADDR); uptime_cycles = litex_read64(TIMER_UPTIME_CYCLES_ADDR);
k_spin_unlock(&lock, key); k_spin_unlock(&lock, key);
return timer_value; return uptime_cycles;
} }
/* tickless kernel is not supported */ /* tickless kernel is not supported */

8
dts/riscv/riscv32-litex-vexriscv.dtsi
View file

@ -87,7 +87,9 @@
0xe0002828 0x10 0xe0002828 0x10
0xe0002838 0x4 0xe0002838 0x4
0xe000283c 0x4 0xe000283c 0x4
0xe0002840 0x4>; 0xe0002840 0x4
0xe0002844 0x4
0xe0002848 0x20>;
reg-names = reg-names =
"load", "load",
"reload", "reload",
@ -96,7 +98,9 @@
"value", "value",
"ev_status", "ev_status",
"ev_pending", "ev_pending",
"ev_enable"; "ev_enable",
"uptime_latch",
"uptime_cycles";
label = "timer0"; label = "timer0";
status = "disabled"; status = "disabled";
}; };