ITE: drviers/pinctrl: Add pinctrl driver for IT8XXX2
Add pinctrl driver for ITE IT8XXX2. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin
Carles Cufí
parent
4c31f24de7
commit
efaeed6cb2
12 changed files with 884 additions and 1 deletions
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@ -6,6 +6,7 @@ zephyr_library_sources(common.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_TELINK_B91 pinctrl_b91.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_TELINK_B91 pinctrl_b91.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RCAR_PFC pfc_rcar.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RCAR_PFC pfc_rcar.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c)
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@ -31,6 +31,7 @@ config PINCTRL_DYNAMIC
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source "drivers/pinctrl/Kconfig.b91"
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source "drivers/pinctrl/Kconfig.b91"
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source "drivers/pinctrl/Kconfig.gd32"
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source "drivers/pinctrl/Kconfig.gd32"
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source "drivers/pinctrl/Kconfig.it8xxx2"
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source "drivers/pinctrl/Kconfig.nrf"
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source "drivers/pinctrl/Kconfig.nrf"
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source "drivers/pinctrl/Kconfig.rcar"
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source "drivers/pinctrl/Kconfig.rcar"
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source "drivers/pinctrl/Kconfig.rpi_pico"
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source "drivers/pinctrl/Kconfig.rpi_pico"
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11
drivers/pinctrl/Kconfig.it8xxx2
Normal file
11
drivers/pinctrl/Kconfig.it8xxx2
Normal file
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@ -0,0 +1,11 @@
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# Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_ITE_IT8XXX2_PINCTRL := ite,it8xxx2-pinctrl
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config PINCTRL_ITE_IT8XXX2
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bool "ITE IT8XXX2 pin controller driver"
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depends on SOC_FAMILY_RISCV_ITE
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default $(dt_compat_enabled,$(DT_COMPAT_ITE_IT8XXX2_PINCTRL))
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help
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Enable IT8XXX2 pin controller driver.
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206
drivers/pinctrl/pinctrl_ite_it8xxx2.c
Normal file
206
drivers/pinctrl/pinctrl_ite_it8xxx2.c
Normal file
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@ -0,0 +1,206 @@
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/*
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* Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_pinctrl_func
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#include <drivers/pinctrl.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR);
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#define GPIO_IT8XXX2_REG_BASE \
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((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
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#define GPIO_GROUP_MEMBERS 8
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struct pinctrl_it8xxx2_config {
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/* gpio port control register (byte mapping to pin) */
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uint8_t *reg_gpcr;
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/* function 3 general control register */
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uintptr_t func3_gcr[GPIO_GROUP_MEMBERS];
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/* function 3 enable mask */
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uint8_t func3_en_mask[GPIO_GROUP_MEMBERS];
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/* function 4 general control register */
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uintptr_t func4_gcr[GPIO_GROUP_MEMBERS];
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/* function 4 enable mask */
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uint8_t func4_en_mask[GPIO_GROUP_MEMBERS];
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/* Input voltage selection */
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uintptr_t volt_sel[GPIO_GROUP_MEMBERS];
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/* Input voltage selection mask */
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uint8_t volt_sel_mask[GPIO_GROUP_MEMBERS];
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};
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static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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uint32_t pincfg = pins->pincfg;
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uint8_t pin = pins->pin;
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volatile uint8_t *reg_gpcr = (uint8_t *)pinctrl_config->reg_gpcr + pin;
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volatile uint8_t *reg_volt_sel = (uint8_t *)(pinctrl_config->volt_sel[pin]);
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/* Setting pull-up or pull-down. */
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switch (IT8XXX2_DT_PINCFG_PUPDR(pincfg)) {
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case IT8XXX2_PULL_PIN_DEFAULT:
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/* No pull-up or pull-down */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
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GPCR_PORT_PIN_MODE_PULLDOWN);
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break;
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case IT8XXX2_PULL_UP:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
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~GPCR_PORT_PIN_MODE_PULLDOWN;
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break;
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case IT8XXX2_PULL_DOWN:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) &
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~GPCR_PORT_PIN_MODE_PULLUP;
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break;
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default:
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LOG_ERR("This pull level is not supported.");
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return -EINVAL;
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}
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/* Setting voltage 3.3V or 1.8V. */
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switch (IT8XXX2_DT_PINCFG_VOLTAGE(pincfg)) {
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case IT8XXX2_VOLTAGE_3V3:
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/* Input voltage selection 3.3V. */
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*reg_volt_sel &= ~pinctrl_config->volt_sel_mask[pin];
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break;
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case IT8XXX2_VOLTAGE_1V8:
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__ASSERT(!(IT8XXX2_DT_PINCFG_PUPDR(pincfg)
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== IT8XXX2_PULL_UP),
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"Don't enable internal pullup if 1.8V voltage is used");
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/* Input voltage selection 1.8V. */
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*reg_volt_sel |= pinctrl_config->volt_sel_mask[pin];
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break;
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default:
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LOG_ERR("The voltage selection is not supported");
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return -EINVAL;
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}
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/* Setting tri-state mode. */
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if (IT8XXX2_DT_PINCFG_IMPEDANCE(pincfg)) {
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*reg_gpcr |= (GPCR_PORT_PIN_MODE_PULLUP |
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GPCR_PORT_PIN_MODE_PULLDOWN);
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}
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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ARG_UNUSED(reg);
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const struct pinctrl_it8xxx2_config *pinctrl_config;
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volatile uint8_t *reg_gpcr;
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volatile uint8_t *reg_func3_gcr;
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volatile uint8_t *reg_func4_gcr;
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uint8_t pin;
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_config = pins[i].pinctrls->config;
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pin = pins[i].pin;
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reg_gpcr = (uint8_t *)pinctrl_config->reg_gpcr + pin;
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reg_func3_gcr = (uint8_t *)(pinctrl_config->func3_gcr[pin]);
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reg_func4_gcr = (uint8_t *)(pinctrl_config->func4_gcr[pin]);
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/* Handle PIN configuration. */
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if (pinctrl_it8xxx2_set(&pins[i])) {
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LOG_ERR("Pin configuration is invalid.");
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return -EINVAL;
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}
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/*
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* If pincfg is input, we don't need to handle
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* alternate function.
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*/
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if (IT8XXX2_DT_PINCFG_INPUT(pins[i].pincfg)) {
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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continue;
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}
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/*
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* Handle alternate function.
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*/
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/* Common settings for alternate function. */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
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GPCR_PORT_PIN_MODE_OUTPUT);
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switch (pins[i].alt_func) {
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case IT8XXX2_ALT_FUNC_1:
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/* Func1: Alternate function has been set above. */
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break;
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case IT8XXX2_ALT_FUNC_2:
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/* Func2: WUI function: turn the pin into an input */
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*reg_gpcr |= GPCR_PORT_PIN_MODE_INPUT;
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break;
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case IT8XXX2_ALT_FUNC_3:
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/*
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* Func3: In addition to the alternate setting above,
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* Func3 also need to set the general control.
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*/
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*reg_func3_gcr |= pinctrl_config->func3_en_mask[pin];
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break;
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case IT8XXX2_ALT_FUNC_4:
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/*
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* Func4: In addition to the alternate setting above,
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* Func4 also need to set the general control.
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*/
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*reg_func4_gcr |= pinctrl_config->func4_en_mask[pin];
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break;
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case IT8XXX2_ALT_DEFAULT:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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*reg_func3_gcr &= ~pinctrl_config->func3_en_mask[pin];
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*reg_func4_gcr &= ~pinctrl_config->func4_en_mask[pin];
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break;
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default:
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LOG_ERR("This function is not supported.");
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return -EINVAL;
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}
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}
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return 0;
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}
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static int pinctrl_it8xxx2_init(const struct device *dev)
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{
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struct gpio_it8xxx2_regs *const gpio_base = GPIO_IT8XXX2_REG_BASE;
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/*
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* The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR.
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* If LPC reset is enabled on GPB7, we have to clear bit2:1
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* to 00b.
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*/
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gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN;
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/*
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* TODO: If UART2 swaps from bit2:1 to bit6:5 in H group, we
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* have to set UART1PSEL = 1 in UART1PMR register.
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*/
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return 0;
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}
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#define PINCTRL_ITE_INIT(inst) \
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static const struct pinctrl_it8xxx2_config pinctrl_it8xxx2_cfg_##inst = { \
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.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR(inst), \
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.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
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.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
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.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
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.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
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.volt_sel = DT_INST_PROP(inst, volt_sel), \
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.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &pinctrl_it8xxx2_init, \
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NULL, \
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NULL, \
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&pinctrl_it8xxx2_cfg_##inst, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(PINCTRL_ITE_INIT)
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37
dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml
Normal file
37
dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml
Normal file
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@ -0,0 +1,37 @@
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# Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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description: ITE IT8XXX2 pin controller function node
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compatible: "ite,it8xxx2-pinctrl-func"
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include: base.yaml
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properties:
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func3-gcr:
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type: array
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required: true
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func3-en-mask:
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type: array
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required: true
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func4-gcr:
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type: array
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required: true
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func4-en-mask:
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type: array
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required: true
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volt-sel:
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type: array
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required: true
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volt-sel-mask:
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type: array
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required: true
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pinmux-cells:
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- pin
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- alt_func
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95
dts/bindings/pinctrl/ite,it8xxx2-pinctrl.yaml
Normal file
95
dts/bindings/pinctrl/ite,it8xxx2-pinctrl.yaml
Normal file
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@ -0,0 +1,95 @@
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# Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The ITE IT8XXX2 pin controller is a node responsible for controlling
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pin function selection and pin properties. For example, you can
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use this node to route UART1 RX and TX setting the alternate
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function on the pin.
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
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'pinctrl' node, as shown in this example:
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/* You can put this in places like a board-pinctrl.dtsi file in
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* your board directory, or a devicetree overlay in your application.
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*/
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/* include pre-defined pins and functions for the SoC used by the board */
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#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
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&pinctrl {
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/* configuration for I2C0 default state */
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i2c0_clk_pb3_default: i2c0_clk_pb3_default {
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pinmuxs = <&pinctrlb 3 IT8XXX2_ALT_FUNC_1>;
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gpio-voltage = "1p8";
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};
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i2c0_data_pb4_default: i2c0_data_pb4_default {
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pinmuxs = <&pinctrlb 4 IT8XXX2_ALT_FUNC_1>;
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gpio-voltage = "1v8";
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};
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/* configuration for UART0 default state */
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uart1_rx_pb0_default: uart1_rx_pb0_default {
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pinmuxs = <&pinctrlb 0 IT8XXX2_ALT_FUNC_3>;
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bias-pull-up;
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};
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uart1_tx_pb1_default: uart1_tx_pb1_default {
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pinmuxs = <&pinctrlb 1 IT8XXX2_ALT_FUNC_3>;
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};
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};
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The 'uart1_rx_pb0_default' child node encodes the pin configurations
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for a particular state of a device; in this case, the default
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(that is, active) sate.
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To link pin configurations with a device, use a pinctrl-N property for some
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number N, like this example you could place in your board's DTS file:
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|
#include "board-pinctrl.dtsi"
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
pinctrl-0 = <&uart1_rx_pb0_default &uart1_tx_pb1_default>;
|
||||||
|
pinctrl-1 = <&uart1_rx_pb0_sleep &uart1_tx_pb1_sleep>;
|
||||||
|
pinctrl-names = "default", "sleep";
|
||||||
|
};
|
||||||
|
|
||||||
|
compatible: "ite,it8xxx2-pinctrl"
|
||||||
|
|
||||||
|
include:
|
||||||
|
- name: base.yaml
|
||||||
|
- name: pincfg-node.yaml
|
||||||
|
child-binding:
|
||||||
|
property-allowlist:
|
||||||
|
- bias-high-impedance
|
||||||
|
- bias-pull-pin-default
|
||||||
|
- bias-pull-up
|
||||||
|
- bias-pull-down
|
||||||
|
- input-enable
|
||||||
|
|
||||||
|
child-binding:
|
||||||
|
description: |
|
||||||
|
This binding gives a base representation of the ITE IT8XXX2 pins configration.
|
||||||
|
properties:
|
||||||
|
pinmuxs:
|
||||||
|
required: true
|
||||||
|
type: phandle-array
|
||||||
|
description: |
|
||||||
|
ITE IT8XXX2 pin's configuration (pinctrl node, pin and function).
|
||||||
|
|
||||||
|
gpio-voltage:
|
||||||
|
required: false
|
||||||
|
type: string
|
||||||
|
description: |
|
||||||
|
Pin input voltage selection 3.3V or 1.8V. All gpio pins support 3.3V.
|
||||||
|
This property only needs to be configured if the board specifies a
|
||||||
|
pin as 1.8V. So the default is 3.3V
|
||||||
|
default: "3v3"
|
||||||
|
enum:
|
||||||
|
- "3v3"
|
||||||
|
- "1v8"
|
||||||
|
|
@ -69,6 +69,262 @@
|
||||||
write-block-size = <4>;
|
write-block-size = <4>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pinctrl: pin-controller {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
status = "okay";
|
||||||
|
label = "PINCTRL";
|
||||||
|
|
||||||
|
pinctrla: pinctrl@f01610 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01610 8>; /* GPCR */
|
||||||
|
label = "PINCTRLA";
|
||||||
|
func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
0xf02032 0xf02032 0xf016f0 0xf016f0>;
|
||||||
|
func3-en-mask = <0 0 0 0
|
||||||
|
0x02 0x02 0x10 0x0C >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC >;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
0xf016e9 0xf016e9 0xf016e9 0xf016e9>;
|
||||||
|
volt-sel-mask = <0 0 0 0
|
||||||
|
0x1 0x02 0x20 0x40 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrlb: pinctrl@f01618 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01618 8>; /* GPCR */
|
||||||
|
label = "PINCTRLB";
|
||||||
|
func3-gcr = <0xf016f5 0xf016f5 NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC 0xf01600>;
|
||||||
|
func3-en-mask = <0x01 0x02 0 0
|
||||||
|
0 0 0 0x02 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC 0xf016f1>;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0x40 >;
|
||||||
|
volt-sel = <NO_FUNC NO_FUNC NO_FUNC 0xf016e7
|
||||||
|
0xf016e7 0xf016e4 0xf016e4 0xf016e9>;
|
||||||
|
volt-sel-mask = <0 0 0 0x02
|
||||||
|
0x01 0x80 0x40 0x10 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrlc: pinctrl@f01620 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01620 8>; /* GPCR */
|
||||||
|
label = "PINCTRLC";
|
||||||
|
func3-gcr = <NO_FUNC NO_FUNC NO_FUNC 0xf016f0
|
||||||
|
NO_FUNC 0xf016f0 NO_FUNC 0xf016f3>;
|
||||||
|
func3-en-mask = <0 0 0 0x10
|
||||||
|
0 0x10 0 0x02 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC 0xf016f6>;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0x80 >;
|
||||||
|
volt-sel = <0xf016e7 0xf016e4 0xf016e4 NO_FUNC
|
||||||
|
0xf016e9 NO_FUNC 0xf016e9 0xf016e4>;
|
||||||
|
volt-sel-mask = <0x80 0x20 0x10 0
|
||||||
|
0x04 0 0x08 0x08 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrld: pinctrl@f01628 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01628 8>; /* GPCR */
|
||||||
|
label = "PINCTRLD";
|
||||||
|
func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC 0xf016f0 NO_FUNC NO_FUNC>;
|
||||||
|
func3-en-mask = <0 0 0 0
|
||||||
|
0 0x02 0 0 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016e4 0xf016e4 0xf016e4 0xf016e5
|
||||||
|
0xf016e5 0xf016e7 0xf016e7 0xf016e7>;
|
||||||
|
volt-sel-mask = <0x04 0x02 0x01 0x80
|
||||||
|
0x40 0x10 0x20 0x40 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrle: pinctrl@f01630 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01630 8>; /* GPCR */
|
||||||
|
label = "PINCTRLE";
|
||||||
|
func3-gcr = <0xf02032 NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC 0xf016f0 NO_FUNC 0xf02032>;
|
||||||
|
func3-en-mask = <0x01 0 0 0
|
||||||
|
0 0x08 0 0x01 >;
|
||||||
|
func4-gcr = <0xf016f3 NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC >;
|
||||||
|
func4-en-mask = <0x01 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016e5 0xf016d4 0xf016d4 NO_FUNC
|
||||||
|
0xf016e7 0xf016e7 0xf016e5 0xf016e5>;
|
||||||
|
volt-sel-mask = <0x20 0x40 0x80 0
|
||||||
|
0x04 0x08 0x10 0x08 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrlf: pinctrl@f01638 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01638 8>; /* GPCR */
|
||||||
|
label = "PINCTRLF";
|
||||||
|
func3-gcr = <NO_FUNC NO_FUNC 0xf016f0 0xf016f0
|
||||||
|
NO_FUNC NO_FUNC 0xf016f1 0xf016f1>;
|
||||||
|
func3-en-mask = <0 0 0x02 0x02
|
||||||
|
0 0 0x10 0x10 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC 0xf02046 0xf02046
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC >;
|
||||||
|
func4-en-mask = <0 0 0x40 0x40
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016d4 0xf016d4 0xf016e5 0xf016e5
|
||||||
|
0xf016e5 0xf016e6 0xf016e6 0xf016e6>;
|
||||||
|
volt-sel-mask = <0x10 0x20 0x04 0x02
|
||||||
|
0x01 0x80 0x40 0x20 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrlg: pinctrl@f01640 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01640 8>; /* GPCR */
|
||||||
|
label = "PINCTRLG";
|
||||||
|
func3-gcr = <0xf016f0 0xf016f0 0xf016f0 NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC 0xf016f0 NO_FUNC>;
|
||||||
|
func3-en-mask = <0x20 0x08 0x10 0
|
||||||
|
0 0 0x02 0 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016d4 0xf016e6 0xf016d4 NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC 0xf016e6 NO_FUNC>;
|
||||||
|
volt-sel-mask = <0x04 0x10 0x08 0
|
||||||
|
0 0 0x08 0 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrlh: pinctrl@f01648 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01648 8>; /* GPCR */
|
||||||
|
label = "PINCTRLH";
|
||||||
|
func3-gcr = <NO_FUNC 0xf016f1 0xf016f1 NO_FUNC
|
||||||
|
NO_FUNC 0xf016f5 0xf016f5 NO_FUNC>;
|
||||||
|
func3-en-mask = <0 0x20 0x20 0
|
||||||
|
0 0x04 0x08 0 >;
|
||||||
|
func4-gcr = <NO_FUNC 0xf016f5 0xf016f5 NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func4-en-mask = <0 0x04 0x08 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016e6 0xf016e6 0xf016e6 NO_FUNC
|
||||||
|
NO_FUNC 0xf016d3 0xf016d4 NO_FUNC>;
|
||||||
|
volt-sel-mask = <0x04 0x02 0x01 0
|
||||||
|
0 0x80 0x01 0 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrli: pinctrl@f01650 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01650 8>; /* GPCR */
|
||||||
|
label = "PINCTRLI";
|
||||||
|
func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC 0xf016f0 0xf016f0 0xf016f0>;
|
||||||
|
func3-en-mask = <0 0 0 0
|
||||||
|
0 0x08 0x08 0x08 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC >;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016d3 0xf016e8 0xf016e8 0xf016e8
|
||||||
|
0xf016e8 0xf016d3 0xf016d3 0xf016d3>;
|
||||||
|
volt-sel-mask = <0x08 0x10 0x20 0x40
|
||||||
|
0x80 0x10 0x20 0x40 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrlj: pinctrl@f01658 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01658 8>; /* GPCR */
|
||||||
|
label = "PINCTRLJ";
|
||||||
|
func3-gcr = <0xf016f4 NO_FUNC 0xf016f4 0xf016f4
|
||||||
|
0xf016f0 0xf016f0 NO_FUNC NO_FUNC>;
|
||||||
|
func3-en-mask = <0x01 0 0x01 0x02
|
||||||
|
0x02 0x03 0 0 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016e8 0xf016e8 0xf016e8 0xf016e8
|
||||||
|
0xf016d3 0xf016d3 0xf016d3 0xf016d7>;
|
||||||
|
volt-sel-mask = <0x01 0x02 0x04 0x08
|
||||||
|
0x01 0x02 0x04 0x04 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrlk: pinctrl@f01690 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01690 8>; /* GPCR */
|
||||||
|
label = "PINCTRLK";
|
||||||
|
func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func3-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016d2 0xf016d2 0xf016d2 0xf016d2
|
||||||
|
0xf016d2 0xf016d2 0xf016d2 0xf016d2>;
|
||||||
|
volt-sel-mask = <0x01 0x02 0x04 0x08
|
||||||
|
0x10 0x20 0x40 0x80 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrll: pinctrl@f01698 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f01698 8>; /* GPCR */
|
||||||
|
label = "PINCTRLL";
|
||||||
|
func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func3-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016d1 0xf016d1 0xf016d1 0xf016d1
|
||||||
|
0xf016d1 0xf016d1 0xf016d1 0xf016d1>;
|
||||||
|
volt-sel-mask = <0x01 0x02 0x04 0x08
|
||||||
|
0x10 0x20 0x40 0x80 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrlm: pinctrl@f016a0 {
|
||||||
|
compatible = "ite,it8xxx2-pinctrl-func";
|
||||||
|
reg = <0x00f016a0 8>; /* GPCR */
|
||||||
|
label = "PINCTRLM";
|
||||||
|
func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func3-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
|
||||||
|
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
|
||||||
|
func4-en-mask = <0 0 0 0
|
||||||
|
0 0 0 0 >;
|
||||||
|
volt-sel = <0xf016ed 0xf016ed 0xf016ed 0xf016ed
|
||||||
|
0xf016ed 0xf016ed 0xf016ed NO_FUNC >;
|
||||||
|
volt-sel-mask = <0x10 0x10 0x10 0x10
|
||||||
|
0x10 0x10 0x10 0 >;
|
||||||
|
#pinmux-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
pinmuxa: pinmux@f01610 {
|
pinmuxa: pinmux@f01610 {
|
||||||
compatible = "ite,it8xxx2-pinmux";
|
compatible = "ite,it8xxx2-pinmux";
|
||||||
reg = <0x00f01610 0x0008>;
|
reg = <0x00f01610 0x0008>;
|
||||||
|
|
@ -485,6 +741,12 @@
|
||||||
interrupt-parent = <&intc>;
|
interrupt-parent = <&intc>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
gpiogcr: gpio-gcr@f01600 {
|
||||||
|
compatible = "ite,it8xxx2-gpiogcr";
|
||||||
|
reg = <0x00f01600 0x100>;
|
||||||
|
label = "GPIO_GCR";
|
||||||
|
};
|
||||||
|
|
||||||
gpioa: gpio@f01601 {
|
gpioa: gpio@f01601 {
|
||||||
compatible = "ite,it8xxx2-gpio";
|
compatible = "ite,it8xxx2-gpio";
|
||||||
reg = <0x00f01601 1 /* GPDR (set) */
|
reg = <0x00f01601 1 /* GPDR (set) */
|
||||||
|
|
|
||||||
|
|
@ -15,4 +15,13 @@
|
||||||
#define IT8XXX2_PINMUX_FUNC_4 3
|
#define IT8XXX2_PINMUX_FUNC_4 3
|
||||||
#define IT8XXX2_PINMUX_PINS 8
|
#define IT8XXX2_PINMUX_PINS 8
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PIN alternate function.
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_ALT_FUNC_1 0U
|
||||||
|
#define IT8XXX2_ALT_FUNC_2 1U
|
||||||
|
#define IT8XXX2_ALT_FUNC_3 2U
|
||||||
|
#define IT8XXX2_ALT_FUNC_4 3U
|
||||||
|
#define IT8XXX2_ALT_DEFAULT 4U
|
||||||
|
|
||||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IT8XXX2_PINCTRL_H_ */
|
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IT8XXX2_PINCTRL_H_ */
|
||||||
|
|
|
||||||
|
|
@ -86,6 +86,17 @@ IT8XXX2_REG_SIZE_CHECK(espi_queue1_regs, 0xc0);
|
||||||
IT8XXX2_REG_OFFSET_CHECK(espi_queue1_regs, UPSTREAM_DATA, 0x00);
|
IT8XXX2_REG_OFFSET_CHECK(espi_queue1_regs, UPSTREAM_DATA, 0x00);
|
||||||
IT8XXX2_REG_OFFSET_CHECK(espi_queue1_regs, PUT_FLASH_NP_DATA, 0x80);
|
IT8XXX2_REG_OFFSET_CHECK(espi_queue1_regs, PUT_FLASH_NP_DATA, 0x80);
|
||||||
|
|
||||||
|
/* GPIO register structure check */
|
||||||
|
IT8XXX2_REG_SIZE_CHECK(gpio_it8xxx2_regs, 0x100);
|
||||||
|
IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR, 0x00);
|
||||||
|
IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR31, 0xD5);
|
||||||
|
IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR18, 0xE2);
|
||||||
|
IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR21, 0xE6);
|
||||||
|
IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR29, 0xEE);
|
||||||
|
IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR2, 0xF1);
|
||||||
|
IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR7, 0xF6);
|
||||||
|
IT8XXX2_REG_OFFSET_CHECK(gpio_it8xxx2_regs, GPIO_GCR14, 0xFD);
|
||||||
|
|
||||||
/* GCTRL register structure check */
|
/* GCTRL register structure check */
|
||||||
IT8XXX2_REG_SIZE_CHECK(gctrl_it8xxx2_regs, 0x88);
|
IT8XXX2_REG_SIZE_CHECK(gctrl_it8xxx2_regs, 0x88);
|
||||||
IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_RSTS, 0x06);
|
IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_RSTS, 0x06);
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
|
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
|
|
@ -1444,6 +1444,101 @@ struct flash_it8xxx2_regs {
|
||||||
#define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18)
|
#define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18)
|
||||||
#define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19)
|
#define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19)
|
||||||
|
|
||||||
|
/**
|
||||||
|
*
|
||||||
|
* (16xxh) General Purpose I/O Port (GPIO) registers
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#ifndef __ASSEMBLER__
|
||||||
|
struct gpio_it8xxx2_regs {
|
||||||
|
/* 0x00: General Control */
|
||||||
|
volatile uint8_t GPIO_GCR;
|
||||||
|
/* 0x01-D0: Reserved1 */
|
||||||
|
volatile uint8_t reserved1[208];
|
||||||
|
/* 0xD1: General Control 25 */
|
||||||
|
volatile uint8_t GPIO_GCR25;
|
||||||
|
/* 0xD2: General Control 26 */
|
||||||
|
volatile uint8_t GPIO_GCR26;
|
||||||
|
/* 0xD3: General Control 27 */
|
||||||
|
volatile uint8_t GPIO_GCR27;
|
||||||
|
/* 0xD4: General Control 28 */
|
||||||
|
volatile uint8_t GPIO_GCR28;
|
||||||
|
/* 0xD5: General Control 31 */
|
||||||
|
volatile uint8_t GPIO_GCR31;
|
||||||
|
/* 0xD6: General Control 32 */
|
||||||
|
volatile uint8_t GPIO_GCR32;
|
||||||
|
/* 0xD7: General Control 33 */
|
||||||
|
volatile uint8_t GPIO_GCR33;
|
||||||
|
/* 0xD8-0xDF: Reserved2 */
|
||||||
|
volatile uint8_t reserved2[8];
|
||||||
|
/* 0xE0: General Control 16 */
|
||||||
|
volatile uint8_t GPIO_GCR16;
|
||||||
|
/* 0xE1: General Control 17 */
|
||||||
|
volatile uint8_t GPIO_GCR17;
|
||||||
|
/* 0xE2: General Control 18 */
|
||||||
|
volatile uint8_t GPIO_GCR18;
|
||||||
|
/* 0xE3: Reserved3 */
|
||||||
|
volatile uint8_t reserved3;
|
||||||
|
/* 0xE4: General Control 19 */
|
||||||
|
volatile uint8_t GPIO_GCR19;
|
||||||
|
/* 0xE5: General Control 20 */
|
||||||
|
volatile uint8_t GPIO_GCR20;
|
||||||
|
/* 0xE6: General Control 21 */
|
||||||
|
volatile uint8_t GPIO_GCR21;
|
||||||
|
/* 0xE7: General Control 22 */
|
||||||
|
volatile uint8_t GPIO_GCR22;
|
||||||
|
/* 0xE8: General Control 23 */
|
||||||
|
volatile uint8_t GPIO_GCR23;
|
||||||
|
/* 0xE9: General Control 24 */
|
||||||
|
volatile uint8_t GPIO_GCR24;
|
||||||
|
/* 0xEA-0xEC: Reserved4 */
|
||||||
|
volatile uint8_t reserved4[3];
|
||||||
|
/* 0xED: General Control 30 */
|
||||||
|
volatile uint8_t GPIO_GCR30;
|
||||||
|
/* 0xEE: General Control 29 */
|
||||||
|
volatile uint8_t GPIO_GCR29;
|
||||||
|
/* 0xEF: Reserved5 */
|
||||||
|
volatile uint8_t reserved5;
|
||||||
|
/* 0xF0: General Control 1 */
|
||||||
|
volatile uint8_t GPIO_GCR1;
|
||||||
|
/* 0xF1: General Control 2 */
|
||||||
|
volatile uint8_t GPIO_GCR2;
|
||||||
|
/* 0xF2: General Control 3 */
|
||||||
|
volatile uint8_t GPIO_GCR3;
|
||||||
|
/* 0xF3: General Control 4 */
|
||||||
|
volatile uint8_t GPIO_GCR4;
|
||||||
|
/* 0xF4: General Control 5 */
|
||||||
|
volatile uint8_t GPIO_GCR5;
|
||||||
|
/* 0xF5: General Control 6 */
|
||||||
|
volatile uint8_t GPIO_GCR6;
|
||||||
|
/* 0xF6: General Control 7 */
|
||||||
|
volatile uint8_t GPIO_GCR7;
|
||||||
|
/* 0xF7: General Control 8 */
|
||||||
|
volatile uint8_t GPIO_GCR8;
|
||||||
|
/* 0xF8: General Control 9 */
|
||||||
|
volatile uint8_t GPIO_GCR9;
|
||||||
|
/* 0xF9: General Control 10 */
|
||||||
|
volatile uint8_t GPIO_GCR10;
|
||||||
|
/* 0xFA: General Control 11 */
|
||||||
|
volatile uint8_t GPIO_GCR11;
|
||||||
|
/* 0xFB: General Control 12 */
|
||||||
|
volatile uint8_t GPIO_GCR12;
|
||||||
|
/* 0xFC: General Control 13 */
|
||||||
|
volatile uint8_t GPIO_GCR13;
|
||||||
|
/* 0xFD: General Control 14 */
|
||||||
|
volatile uint8_t GPIO_GCR14;
|
||||||
|
/* 0xFE: General Control 15 */
|
||||||
|
volatile uint8_t GPIO_GCR15;
|
||||||
|
/* 0xFF: Power Good Watch Control */
|
||||||
|
volatile uint8_t GPIO_PGWCR;
|
||||||
|
};
|
||||||
|
#endif /* !__ASSEMBLER__ */
|
||||||
|
|
||||||
|
/* GPIO register fields */
|
||||||
|
/* 0x00: General Control */
|
||||||
|
#define IT8XXX2_GPIO_LPCRSTEN (BIT(2) | BIT(1))
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
*
|
*
|
||||||
* (19xxh) Analog to Digital Converter (ADC) registers
|
* (19xxh) Analog to Digital Converter (ADC) registers
|
||||||
|
|
|
||||||
152
soc/riscv/riscv-ite/common/pinctrl_soc.h
Normal file
152
soc/riscv/riscv-ite/common/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,152 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022 ITE Technology Corporation.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ZEPHYR_SOC_RISCV_ITE_IT8XXX2_COMMON_PINCTRL_SOC_H_
|
||||||
|
#define ZEPHYR_SOC_RISCV_ITE_IT8XXX2_COMMON_PINCTRL_SOC_H_
|
||||||
|
|
||||||
|
#include <zephyr/devicetree.h>
|
||||||
|
#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
|
||||||
|
#include <zephyr/zephyr/types.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ITE IT8XXX2 pin type.
|
||||||
|
*/
|
||||||
|
struct pinctrl_soc_pin {
|
||||||
|
/* Pinmux control group */
|
||||||
|
const struct device *pinctrls;
|
||||||
|
/* Pin configuration (impedance, pullup/down, voltate selection, input). */
|
||||||
|
uint32_t pincfg;
|
||||||
|
/* GPIO pin */
|
||||||
|
uint8_t pin;
|
||||||
|
/* Alternate function */
|
||||||
|
uint8_t alt_func;
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PIN configuration bitfield.
|
||||||
|
*
|
||||||
|
* Pin configuration is coded with the following
|
||||||
|
* fields.
|
||||||
|
* Pin impedance config [ 0 ]
|
||||||
|
* Pin pull-up/down config [ 4 : 5 ]
|
||||||
|
* Pin voltage selection [ 8 ]
|
||||||
|
* Pin input enable config [ 12 ]
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_HIGH_IMPEDANCE 0x1U
|
||||||
|
#define IT8XXX2_PULL_PIN_DEFAULT 0x0U
|
||||||
|
#define IT8XXX2_PULL_UP 0x1U
|
||||||
|
#define IT8XXX2_PULL_DOWN 0x2U
|
||||||
|
#define IT8XXX2_VOLTAGE_3V3 0x0U
|
||||||
|
#define IT8XXX2_VOLTAGE_1V8 0x1U
|
||||||
|
#define IT8XXX2_INPUT_ENABLE 0x1U
|
||||||
|
|
||||||
|
/* Pin tri-state mode. */
|
||||||
|
#define IT8XXX2_IMPEDANCE_SHIFT 0U
|
||||||
|
#define IT8XXX2_IMPEDANCE_MASK 0x1U
|
||||||
|
/* Pin pull-up or pull-down */
|
||||||
|
#define IT8XXX2_PUPDR_SHIFT 4U
|
||||||
|
#define IT8XXX2_PUPDR_MASK 0x3U
|
||||||
|
/* Pin 3.3V or 1.8V */
|
||||||
|
#define IT8XXX2_VOLTAGE_SHIFT 8U
|
||||||
|
#define IT8XXX2_VOLTAGE_MASK 0x1U
|
||||||
|
/* Pin INPUT enable or disable */
|
||||||
|
#define IT8XXX2_INPUT_SHIFT 12U
|
||||||
|
#define IT8XXX2_INPUT_MASK 0x1U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to obtain configuration of tri-state.
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_DT_PINCFG_IMPEDANCE(__mode) \
|
||||||
|
(((__mode) >> IT8XXX2_IMPEDANCE_SHIFT) & IT8XXX2_IMPEDANCE_MASK)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to obtain configuration of pull-up or pull-down.
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_DT_PINCFG_PUPDR(__mode) \
|
||||||
|
(((__mode) >> IT8XXX2_PUPDR_SHIFT) & IT8XXX2_PUPDR_MASK)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to obtain input voltage selection.
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_DT_PINCFG_VOLTAGE(__mode) \
|
||||||
|
(((__mode) >> IT8XXX2_VOLTAGE_SHIFT) & IT8XXX2_VOLTAGE_MASK)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to obtain input enable.
|
||||||
|
*/
|
||||||
|
#define IT8XXX2_DT_PINCFG_INPUT(__mode) \
|
||||||
|
(((__mode) >> IT8XXX2_INPUT_SHIFT) & IT8XXX2_INPUT_MASK)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
|
||||||
|
*
|
||||||
|
* @param node_id Node identifier.
|
||||||
|
*/
|
||||||
|
#define Z_PINCTRL_IT8XXX2_PINCFG_INIT(node_id) \
|
||||||
|
(((IT8XXX2_HIGH_IMPEDANCE * DT_PROP(node_id, bias_high_impedance)) \
|
||||||
|
<< IT8XXX2_IMPEDANCE_SHIFT) | \
|
||||||
|
((IT8XXX2_PULL_PIN_DEFAULT * DT_PROP(node_id, bias_pull_pin_default)) \
|
||||||
|
<< IT8XXX2_PUPDR_SHIFT) | \
|
||||||
|
((IT8XXX2_PULL_UP * DT_PROP(node_id, bias_pull_up)) \
|
||||||
|
<< IT8XXX2_PUPDR_SHIFT) | \
|
||||||
|
((IT8XXX2_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) \
|
||||||
|
<< IT8XXX2_PUPDR_SHIFT) | \
|
||||||
|
((IT8XXX2_VOLTAGE_1V8 * DT_ENUM_IDX(node_id, gpio_voltage)) \
|
||||||
|
<< IT8XXX2_VOLTAGE_SHIFT) | \
|
||||||
|
((IT8XXX2_INPUT_ENABLE * DT_PROP(node_id, input_enable)) \
|
||||||
|
<< IT8XXX2_INPUT_SHIFT))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to initialize pinctrls of pinmuxs field in #pinctrl_pin_t.
|
||||||
|
*
|
||||||
|
* @param node_id Node identifier.
|
||||||
|
*/
|
||||||
|
#define Z_PINCTRL_IT8XXX2_PINCTRL_INIT(node_id) \
|
||||||
|
DEVICE_DT_GET(DT_PHANDLE(node_id, pinmuxs))
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to initialize pin of pinmuxs field in #pinctrl_pin_t.
|
||||||
|
*
|
||||||
|
* @param node_id Node identifier.
|
||||||
|
*/
|
||||||
|
#define Z_PINCTRL_IT8XXX2_PIN_INIT(node_id) \
|
||||||
|
DT_PHA(node_id, pinmuxs, pin)
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to initialize alt_func of pinmuxs field in #pinctrl_pin_t.
|
||||||
|
*
|
||||||
|
* @param node_id Node identifier.
|
||||||
|
*/
|
||||||
|
#define Z_PINCTRL_IT8XXX2_ALT_INIT(node_id) \
|
||||||
|
DT_PHA(node_id, pinmuxs, alt_func)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to initialize each pin.
|
||||||
|
*
|
||||||
|
* @param node_id Node identifier.
|
||||||
|
* @param prop Property name.
|
||||||
|
* @param idx Property entry index.
|
||||||
|
*/
|
||||||
|
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||||
|
{ .pinctrls = Z_PINCTRL_IT8XXX2_PINCTRL_INIT( \
|
||||||
|
DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||||
|
.pincfg = Z_PINCTRL_IT8XXX2_PINCFG_INIT( \
|
||||||
|
DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||||
|
.pin = Z_PINCTRL_IT8XXX2_PIN_INIT( \
|
||||||
|
DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||||
|
.alt_func = Z_PINCTRL_IT8XXX2_ALT_INIT( \
|
||||||
|
DT_PROP_BY_IDX(node_id, prop, idx)), },
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Utility macro to initialize state pins contained in a given property.
|
||||||
|
*
|
||||||
|
* @param node_id Node identifier.
|
||||||
|
* @param prop Property name describing state pins.
|
||||||
|
*/
|
||||||
|
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||||
|
{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
|
||||||
|
|
||||||
|
#endif /* ZEPHYR_SOC_RISCV_ITE_IT8XXX2_COMMON_PINCTRL_SOC_H_ */
|
||||||
|
|
@ -88,6 +88,9 @@ config PECI_ITE_IT8XXX2
|
||||||
depends on PECI
|
depends on PECI
|
||||||
select PECI_INTERRUPT_DRIVEN
|
select PECI_INTERRUPT_DRIVEN
|
||||||
|
|
||||||
|
config PINCTRL
|
||||||
|
default y
|
||||||
|
|
||||||
if ITE_IT8XXX2_INTC
|
if ITE_IT8XXX2_INTC
|
||||||
config NUM_IRQS
|
config NUM_IRQS
|
||||||
default 185
|
default 185
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue