ITE: drviers/pinctrl: Add pinctrl driver for IT8XXX2
Add pinctrl driver for ITE IT8XXX2. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin
Carles Cufí
parent
4c31f24de7
commit
efaeed6cb2
12 changed files with 884 additions and 1 deletions
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@ -6,6 +6,7 @@ zephyr_library_sources(common.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_TELINK_B91 pinctrl_b91.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RCAR_PFC pfc_rcar.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c)
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@ -31,6 +31,7 @@ config PINCTRL_DYNAMIC
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source "drivers/pinctrl/Kconfig.b91"
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source "drivers/pinctrl/Kconfig.gd32"
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source "drivers/pinctrl/Kconfig.it8xxx2"
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source "drivers/pinctrl/Kconfig.nrf"
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source "drivers/pinctrl/Kconfig.rcar"
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source "drivers/pinctrl/Kconfig.rpi_pico"
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11
drivers/pinctrl/Kconfig.it8xxx2
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11
drivers/pinctrl/Kconfig.it8xxx2
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@ -0,0 +1,11 @@
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# Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_ITE_IT8XXX2_PINCTRL := ite,it8xxx2-pinctrl
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config PINCTRL_ITE_IT8XXX2
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bool "ITE IT8XXX2 pin controller driver"
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depends on SOC_FAMILY_RISCV_ITE
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default $(dt_compat_enabled,$(DT_COMPAT_ITE_IT8XXX2_PINCTRL))
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help
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Enable IT8XXX2 pin controller driver.
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206
drivers/pinctrl/pinctrl_ite_it8xxx2.c
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206
drivers/pinctrl/pinctrl_ite_it8xxx2.c
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@ -0,0 +1,206 @@
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/*
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* Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_pinctrl_func
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#include <drivers/pinctrl.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR);
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#define GPIO_IT8XXX2_REG_BASE \
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((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
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#define GPIO_GROUP_MEMBERS 8
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struct pinctrl_it8xxx2_config {
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/* gpio port control register (byte mapping to pin) */
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uint8_t *reg_gpcr;
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/* function 3 general control register */
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uintptr_t func3_gcr[GPIO_GROUP_MEMBERS];
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/* function 3 enable mask */
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uint8_t func3_en_mask[GPIO_GROUP_MEMBERS];
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/* function 4 general control register */
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uintptr_t func4_gcr[GPIO_GROUP_MEMBERS];
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/* function 4 enable mask */
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uint8_t func4_en_mask[GPIO_GROUP_MEMBERS];
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/* Input voltage selection */
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uintptr_t volt_sel[GPIO_GROUP_MEMBERS];
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/* Input voltage selection mask */
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uint8_t volt_sel_mask[GPIO_GROUP_MEMBERS];
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};
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static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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uint32_t pincfg = pins->pincfg;
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uint8_t pin = pins->pin;
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volatile uint8_t *reg_gpcr = (uint8_t *)pinctrl_config->reg_gpcr + pin;
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volatile uint8_t *reg_volt_sel = (uint8_t *)(pinctrl_config->volt_sel[pin]);
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/* Setting pull-up or pull-down. */
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switch (IT8XXX2_DT_PINCFG_PUPDR(pincfg)) {
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case IT8XXX2_PULL_PIN_DEFAULT:
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/* No pull-up or pull-down */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
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GPCR_PORT_PIN_MODE_PULLDOWN);
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break;
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case IT8XXX2_PULL_UP:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
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~GPCR_PORT_PIN_MODE_PULLDOWN;
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break;
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case IT8XXX2_PULL_DOWN:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) &
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~GPCR_PORT_PIN_MODE_PULLUP;
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break;
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default:
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LOG_ERR("This pull level is not supported.");
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return -EINVAL;
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}
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/* Setting voltage 3.3V or 1.8V. */
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switch (IT8XXX2_DT_PINCFG_VOLTAGE(pincfg)) {
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case IT8XXX2_VOLTAGE_3V3:
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/* Input voltage selection 3.3V. */
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*reg_volt_sel &= ~pinctrl_config->volt_sel_mask[pin];
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break;
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case IT8XXX2_VOLTAGE_1V8:
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__ASSERT(!(IT8XXX2_DT_PINCFG_PUPDR(pincfg)
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== IT8XXX2_PULL_UP),
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"Don't enable internal pullup if 1.8V voltage is used");
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/* Input voltage selection 1.8V. */
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*reg_volt_sel |= pinctrl_config->volt_sel_mask[pin];
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break;
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default:
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LOG_ERR("The voltage selection is not supported");
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return -EINVAL;
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}
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/* Setting tri-state mode. */
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if (IT8XXX2_DT_PINCFG_IMPEDANCE(pincfg)) {
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*reg_gpcr |= (GPCR_PORT_PIN_MODE_PULLUP |
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GPCR_PORT_PIN_MODE_PULLDOWN);
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}
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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ARG_UNUSED(reg);
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const struct pinctrl_it8xxx2_config *pinctrl_config;
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volatile uint8_t *reg_gpcr;
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volatile uint8_t *reg_func3_gcr;
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volatile uint8_t *reg_func4_gcr;
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uint8_t pin;
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_config = pins[i].pinctrls->config;
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pin = pins[i].pin;
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reg_gpcr = (uint8_t *)pinctrl_config->reg_gpcr + pin;
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reg_func3_gcr = (uint8_t *)(pinctrl_config->func3_gcr[pin]);
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reg_func4_gcr = (uint8_t *)(pinctrl_config->func4_gcr[pin]);
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/* Handle PIN configuration. */
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if (pinctrl_it8xxx2_set(&pins[i])) {
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LOG_ERR("Pin configuration is invalid.");
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return -EINVAL;
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}
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/*
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* If pincfg is input, we don't need to handle
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* alternate function.
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*/
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if (IT8XXX2_DT_PINCFG_INPUT(pins[i].pincfg)) {
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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continue;
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}
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/*
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* Handle alternate function.
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*/
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/* Common settings for alternate function. */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
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GPCR_PORT_PIN_MODE_OUTPUT);
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switch (pins[i].alt_func) {
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case IT8XXX2_ALT_FUNC_1:
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/* Func1: Alternate function has been set above. */
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break;
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case IT8XXX2_ALT_FUNC_2:
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/* Func2: WUI function: turn the pin into an input */
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*reg_gpcr |= GPCR_PORT_PIN_MODE_INPUT;
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break;
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case IT8XXX2_ALT_FUNC_3:
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/*
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* Func3: In addition to the alternate setting above,
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* Func3 also need to set the general control.
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*/
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*reg_func3_gcr |= pinctrl_config->func3_en_mask[pin];
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break;
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case IT8XXX2_ALT_FUNC_4:
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/*
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* Func4: In addition to the alternate setting above,
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* Func4 also need to set the general control.
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*/
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*reg_func4_gcr |= pinctrl_config->func4_en_mask[pin];
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break;
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case IT8XXX2_ALT_DEFAULT:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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*reg_func3_gcr &= ~pinctrl_config->func3_en_mask[pin];
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*reg_func4_gcr &= ~pinctrl_config->func4_en_mask[pin];
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break;
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default:
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LOG_ERR("This function is not supported.");
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return -EINVAL;
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}
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}
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return 0;
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}
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static int pinctrl_it8xxx2_init(const struct device *dev)
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{
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struct gpio_it8xxx2_regs *const gpio_base = GPIO_IT8XXX2_REG_BASE;
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/*
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* The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR.
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* If LPC reset is enabled on GPB7, we have to clear bit2:1
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* to 00b.
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*/
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gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN;
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/*
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* TODO: If UART2 swaps from bit2:1 to bit6:5 in H group, we
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* have to set UART1PSEL = 1 in UART1PMR register.
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*/
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return 0;
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}
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#define PINCTRL_ITE_INIT(inst) \
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static const struct pinctrl_it8xxx2_config pinctrl_it8xxx2_cfg_##inst = { \
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.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR(inst), \
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.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
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.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
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.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
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.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
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.volt_sel = DT_INST_PROP(inst, volt_sel), \
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.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &pinctrl_it8xxx2_init, \
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NULL, \
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NULL, \
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&pinctrl_it8xxx2_cfg_##inst, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(PINCTRL_ITE_INIT)
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