diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA b/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA
new file mode 100644
index 00000000000..849ecb8466f
--- /dev/null
+++ b/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA
@@ -0,0 +1,14 @@
+# Nordic Semiconductor nRF5340 Network MCU
+
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NRF5340_CPUNET_QKAA
+
+config SOC
+	default "nRF5340_CPUNET_QKAA"
+
+config NUM_IRQS
+	default 30
+
+endif # SOC_NRF5340_CPUNET_QKAA
diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.soc b/soc/arm/nordic_nrf/nrf53/Kconfig.soc
index e59016528ed..cc3487c933e 100644
--- a/soc/arm/nordic_nrf/nrf53/Kconfig.soc
+++ b/soc/arm/nordic_nrf/nrf53/Kconfig.soc
@@ -48,6 +48,33 @@ config SOC_NRF5340_CPUAPP
 	select HAS_HW_NRF_UARTE1
 	select HAS_HW_NRF_WDT
 
+config SOC_NRF5340_CPUNET
+	depends on SOC_SERIES_NRF53X
+	bool
+	select HAS_HW_NRF_CLOCK
+	select HAS_HW_NRF_DPPIC
+	select HAS_HW_NRF_EGU0
+	select HAS_HW_NRF_GPIO0
+	select HAS_HW_NRF_GPIO1
+	select HAS_HW_NRF_GPIOTE
+	select HAS_HW_NRF_IPC
+	select HAS_HW_NRF_POWER
+	select HAS_HW_NRF_RADIO_BLE_CODED
+	select HAS_HW_NRF_RADIO_IEEE802154
+	select HAS_HW_NRF_RNG
+	select HAS_HW_NRF_RTC0
+	select HAS_HW_NRF_RTC1
+	select HAS_HW_NRF_SPIM0
+	select HAS_HW_NRF_SPIS0
+	select HAS_HW_NRF_TEMP
+	select HAS_HW_NRF_TIMER0
+	select HAS_HW_NRF_TIMER1
+	select HAS_HW_NRF_TIMER2
+	select HAS_HW_NRF_TWIM0
+	select HAS_HW_NRF_TWIS0
+	select HAS_HW_NRF_UARTE0
+	select HAS_HW_NRF_WDT
+
 choice
 	prompt "nRF53x MCU Selection"
 	depends on SOC_SERIES_NRF53X
@@ -56,11 +83,16 @@ config SOC_NRF5340_CPUAPP_QKAA
 	bool "NRF5340_CPUAPP_QKAA"
 	select SOC_NRF5340_CPUAPP
 
+config SOC_NRF5340_CPUNET_QKAA
+	bool "NRF5340_CPUNET_QKAA"
+	select SOC_NRF5340_CPUNET
+
 endchoice
 
 config NRF_ENABLE_CACHE
 	bool "Enable cache"
-	depends on SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE
+	depends on (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) \
+			|| SOC_NRF5340_CPUNET
 	default y
 	help
 	  Instruction and Data cache is available on nRF5340 CPUAPP
diff --git a/soc/arm/nordic_nrf/nrf53/soc.c b/soc/arm/nordic_nrf/nrf53/soc.c
index 81b2dc47c95..2f7e8e2a505 100644
--- a/soc/arm/nordic_nrf/nrf53/soc.c
+++ b/soc/arm/nordic_nrf/nrf53/soc.c
@@ -27,6 +27,8 @@ extern void z_arm_nmi_init(void);
 
 #if defined(CONFIG_SOC_NRF5340_CPUAPP)
 #include <system_nrf5340_application.h>
+#elif defined(CONFIG_SOC_NRF5340_CPUNET)
+#include <system_nrf5340_network.h>
 #else
 #error "Unknown nRF53 SoC."
 #endif
@@ -47,6 +49,9 @@ static int nordicsemi_nrf53_init(struct device *arg)
 	/* Enable the instruction & data cache */
 	NRF_CACHE_S->ENABLE = CACHE_ENABLE_ENABLE_Msk;
 #endif /* CONFIG_SOC_NRF5340_CPUAPP */
+#ifdef CONFIG_SOC_NRF5340_CPUNET
+	NRF_NVMC_NS->ICACHECNF |= NVMC_ICACHECNF_CACHEEN_Enabled;
+#endif /* CONFIG_SOC_NRF5340_CPUNET */
 #endif
 
 #if defined(CONFIG_SOC_NRF5340_CPUAPP) && \
diff --git a/soc/arm/nordic_nrf/nrf53/soc.h b/soc/arm/nordic_nrf/nrf53/soc.h
index cc75b2510bd..d7f3ac5a31f 100644
--- a/soc/arm/nordic_nrf/nrf53/soc.h
+++ b/soc/arm/nordic_nrf/nrf53/soc.h
@@ -21,7 +21,12 @@
 
 #endif /* !_ASMLANGUAGE */
 
+#if defined(CONFIG_SOC_NRF5340_CPUAPP)
 #define FLASH_PAGE_ERASE_MAX_TIME_US  89700UL
 #define FLASH_PAGE_MAX_CNT  256UL
+#elif defined(CONFIG_SOC_NRF5340_CPUNET)
+#define FLASH_PAGE_ERASE_MAX_TIME_US  44850UL
+#define FLASH_PAGE_MAX_CNT  128UL
+#endif
 
 #endif /* _NORDICSEMI_NRF53_SOC_H_ */