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arch: arm: cortex_r: Add userspace support for non-XIP builds

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When running non-XIP, userspace threads need to be able to read .text in
order to execute code.  Cortex-R needs to setup an MPU entry to allow
this, but it must be aligned to a power of 2.  The linker scripts for
other archs follow this same pattern of aligning the location counter,
but outside of an input section.  The linker ignores this and places the
next input section at the LMA of the end of the previous input section.
Avoid this problem by make RODATA the last ROM section.  The MPU_ALIGN
can be moved inside the RODATA input section and correctly pad the
entire ROM section out to a power of 2 boundary.

_image_rom_end_order contains the power of 2 alignment which allow the
soc to set the MPU configuration statically based on the size of the ROM
sections instead of having to do it dynamically.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit is contained in:
Bradley Bolen 2021-05-13 16:58:30 -04:00 • committed by Christopher Friedt
commit ef50545808
1 changed files with 12 additions and 3 deletions
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15
include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld
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@ -108,7 +108,11 @@ SECTIONS
GROUP_START(ROMABLE_REGION)
#if defined(CONFIG_XIP)
_image_rom_start = ROM_ADDR;
#else
_image_rom_start = RAM_ADDR;
#endif
SECTION_PROLOGUE(rom_start,,)
{
@ -175,6 +179,7 @@ SECTIONS
#include <linker/common-rom.ld>
#include <linker/thread-local-storage.ld>
#include <linker/cplusplus-rom.ld>
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{
@ -200,13 +205,17 @@ SECTIONS
* usually 4k aligned.
*/
. = ALIGN(4);
/*
* RODATA must be the last section so that the size of the entire read
* only area will be filled to a power of 2.
*/
MPU_ALIGN(ABSOLUTE(.) - _image_rom_start);
} GROUP_LINK_IN(ROMABLE_REGION)
#include <linker/cplusplus-rom.ld>
_image_rodata_end = .;
MPU_ALIGN(_image_rodata_end -_image_rom_start);
_image_rom_end = .;
_image_rom_end_order = (LOG2CEIL(_image_rom_end) - 1) << 1;
GROUP_END(ROMABLE_REGION)