From eee56a7c10259f9494d515479ca8ebd794a81f2e Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Wed, 26 Apr 2017 15:23:04 +0200 Subject: [PATCH] soc: stm32l4xx: add support for STM32L475XG Add support for STM32L475xG SoC as a preliminary for Discovery IOT board support. stm32l476.dtsi file is now including stm32l475.dtsi since STM32L476 SoC is a STM32L475 SoC with LCD support Change-Id: I7567255e4172231cbf4899474617ecae0cd68d64 Signed-off-by: Erwan Gouriou --- .../stm32l4/Kconfig.defconfig.stm32l475xg | 18 ++++++ arch/arm/soc/st_stm32/stm32l4/Kconfig.soc | 4 ++ dts/arm/st/mem.h | 3 + dts/arm/st/stm32l475.dtsi | 59 +++++++++++++++++++ dts/arm/st/stm32l476.dtsi | 54 +---------------- 5 files changed, 85 insertions(+), 53 deletions(-) create mode 100644 arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg create mode 100644 dts/arm/st/stm32l475.dtsi diff --git a/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg b/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg new file mode 100644 index 00000000000..c4b9b1a8858 --- /dev/null +++ b/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg @@ -0,0 +1,18 @@ +# Kconfig - ST Microelectronics STM32L475xG MCU +# +# Copyright (c) 2017 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_STM32L475XG + +config SOC + string + default stm32l475xx + +config NUM_IRQS + int + default 82 + +endif # SOC_STM32L475XG diff --git a/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc b/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc index dd11275808c..69f80ebc27e 100644 --- a/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc +++ b/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc @@ -14,4 +14,8 @@ config SOC_STM32L476XX bool "STM32L476XX" select HAS_STM32CUBE +config SOC_STM32L475XG + bool "STM32L475XG" + select HAS_STM32CUBE + endchoice diff --git a/dts/arm/st/mem.h b/dts/arm/st/mem.h index b4bb13ff4fb..b9628bafebf 100644 --- a/dts/arm/st/mem.h +++ b/dts/arm/st/mem.h @@ -33,6 +33,9 @@ #elif defined(CONFIG_SOC_STM32F429XX) #define DT_FLASH_SIZE __SIZE_K(2048) #define DT_SRAM_SIZE __SIZE_K(256) +#elif defined(CONFIG_SOC_STM32L475XG) +#define DT_FLASH_SIZE __SIZE_K(1024) +#define DT_SRAM_SIZE __SIZE_K(96) #elif defined(CONFIG_SOC_STM32L476XX) #define DT_FLASH_SIZE __SIZE_K(1024) #define DT_SRAM_SIZE __SIZE_K(96) diff --git a/dts/arm/st/stm32l475.dtsi b/dts/arm/st/stm32l475.dtsi new file mode 100644 index 00000000000..19329faaf7a --- /dev/null +++ b/dts/arm/st/stm32l475.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + flash0: flash { + reg = <0x08000000 DT_FLASH_SIZE>; + }; + + sram0: memory { + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + usart1: uart@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + interrupts = <37 0>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + status = "disabled"; + }; + + usart3: uart@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + interrupts = <39 0>; + status = "disabled"; + }; + + uart4: uart@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52 0>; + status = "disabled"; + }; + + uart5: uart@40005000 { + compatible = "st,stm32-uart"; + reg = <0x40005000 0x400>; + interrupts = <53 0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/st/stm32l476.dtsi b/dts/arm/st/stm32l476.dtsi index 19329faaf7a..7b336a2ac28 100644 --- a/dts/arm/st/stm32l476.dtsi +++ b/dts/arm/st/stm32l476.dtsi @@ -4,56 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include -#include - -/ { - flash0: flash { - reg = <0x08000000 DT_FLASH_SIZE>; - }; - - sram0: memory { - reg = <0x20000000 DT_SRAM_SIZE>; - }; - - soc { - usart1: uart@40013800 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40013800 0x400>; - interrupts = <37 0>; - status = "disabled"; - }; - - usart2: uart@40004400 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40004400 0x400>; - interrupts = <38 0>; - status = "disabled"; - }; - - usart3: uart@40004800 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40004800 0x400>; - interrupts = <39 0>; - status = "disabled"; - }; - - uart4: uart@40004c00 { - compatible = "st,stm32-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52 0>; - status = "disabled"; - }; - - uart5: uart@40005000 { - compatible = "st,stm32-uart"; - reg = <0x40005000 0x400>; - interrupts = <53 0>; - status = "disabled"; - }; - }; -}; - -&nvic { - arm,num-irq-priority-bits = <4>; -}; +#include