From ee91ae5a21a5eae69c0c2eee5065265a12199ecd Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Fri, 14 Jan 2022 09:04:28 +0100 Subject: [PATCH] boards: arm: rcar_h3ulcb: add pins definition Add some pins definitions for CAN0 and SCIF1/2. Signed-off-by: Julien Massot --- .../rcar_h3ulcb/rcar_h3ulcb_cr7-pinctrl.dtsi | 33 +++++++++++++++++++ boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts | 3 ++ 2 files changed, 36 insertions(+) create mode 100644 boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7-pinctrl.dtsi diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7-pinctrl.dtsi b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7-pinctrl.dtsi new file mode 100644 index 00000000000..a963552b605 --- /dev/null +++ b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7-pinctrl.dtsi @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022 IoT.bzh + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pfc { + can0_data_a_tx_default: can0_data_a_tx_default { + pin = ; + }; + + can0_data_a_rx_default: can0_data_a_rx_default { + pin = ; + }; + + scif1_data_a_tx_default: scif1_data_a_tx_default { + pin = ; + }; + + scif1_data_a_rx_default: scif1_data_a_rx_default { + pin = ; + }; + + scif2_data_a_tx_default: scif2_data_a_tx_default { + pin = ; + }; + + scif2_data_a_rx_default: scif2_data_a_rx_default { + pin = ; + }; +}; diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts index b2e0d0e291f..7a32384e01e 100644 --- a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts +++ b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include "rcar_h3ulcb_cr7-pinctrl.dtsi" / { model = "Renesas h3ulcb board"; @@ -51,6 +52,8 @@ }; &can0 { + pinctrl-0 = <&can0_data_a_tx_default &can0_data_a_rx_default>; + pinctrl-names = "default"; status = "okay"; };