diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld index 2cf7b64f69b..f9602925969 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld @@ -35,16 +35,16 @@ PROVIDE(_MemErrorHandler = 0x00000000); * data (e.g. stacks) or shared data that is managed with explicit * cache flush/invalidate operations. * - * These macros will set up a segment start address correctly, - * including alignment to a cache line. Be sure to also emit the + * The UNCACHED_RAM_OFFSET will be used before to move the address + * pointer forward or backward so code and data land in correct + * region. Remember to align the memory, and be sure to also emit the * section to ">ram :ram_phdr" or ">ucram :ucram_phdr" as * appropriate. (Forgetting the correct PHDR will actually work, as * the output tooling ignores it, but it will cause the linker to emit * 512MB of unused data into the output file!) * */ -#define SEGSTART_CACHED (ALIGN(64) | 0x20000000) -#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000) +#define UNCACHED_RAM_OFFSET 0x20000000 MEMORY { @@ -115,7 +115,7 @@ MEMORY org = RAM_BASE, len = RAM_SIZE ucram : - org = RAM_BASE - 0x20000000, + org = RAM_BASE - UNCACHED_RAM_OFFSET, len = RAM_SIZE #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST : @@ -429,7 +429,14 @@ SECTIONS _lit4_end = ABSOLUTE(.); } >ram :ram_phdr - .data SEGSTART_UNCACHED : ALIGN(4) + /* + * Address pointer here is at cached ram. + * So need to go into uncached memory region, hence + * the subtraction. + */ + segstart_uncached_data = ALIGN(64) - UNCACHED_RAM_OFFSET; + + .data segstart_uncached_data : ALIGN(4) { _data_start = ABSOLUTE(.); *(.data) @@ -466,22 +473,28 @@ SECTIONS #define ROMABLE_REGION ucram :ucram_phdr #include + /* Going back into cached memory region. */ + segstart_cached_cached = ALIGN(64) + UNCACHED_RAM_OFFSET; + /* This section is cached. By default it contains only declared * thread stacks, but applications can put symbols here too. */ - .cached SEGSTART_CACHED : + .cached segstart_cached_cached : { *(.cached .cached.*) } >ram :ram_phdr - .tm_clone_table SEGSTART_UNCACHED : + /* Going back into un-cached memory region. */ + segstart_uncached_tm_clone_table = ALIGN(64) - UNCACHED_RAM_OFFSET; + + .tm_clone_table segstart_uncached_tm_clone_table : { *(.tm_clone_table) } >ram :ram_phdr . = ALIGN(4096); - .bss SEGSTART_UNCACHED (NOLOAD) : + .bss ALIGN(64) (NOLOAD) : { _bss_start = ABSOLUTE(.); *(.dynsbss) @@ -502,16 +515,17 @@ SECTIONS } >ucram :ucram_phdr /* Re-adjust to the upper mapping for the final symbols below */ - . = SEGSTART_CACHED; + segstart_cached_stack = ALIGN(64) + UNCACHED_RAM_OFFSET; + . = segstart_cached_stack; /* Initial/boot stack lives in the CPU0 interrupt stack */ __stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE; /* These symbols bound the newlib heap, which must be uncached */ - . = SEGSTART_UNCACHED; + segstart_uncached_end = ALIGN(64) - UNCACHED_RAM_OFFSET; + . = segstart_uncached_end; _end = .; . = L2_SRAM_BASE + L2_SRAM_SIZE; - . = SEGSTART_UNCACHED; _heap_sentry = .; /* dma buffers */ diff --git a/soc/xtensa/intel_adsp/cavs_v18/linker.ld b/soc/xtensa/intel_adsp/cavs_v18/linker.ld index 964fcbfea19..ba128dec701 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v18/linker.ld @@ -35,16 +35,16 @@ PROVIDE(_MemErrorHandler = 0x00000000); * data (e.g. stacks) or shared data that is managed with explicit * cache flush/invalidate operations. * - * These macros will set up a segment start address correctly, - * including alignment to a cache line. Be sure to also emit the + * The UNCACHED_RAM_OFFSET will be used before to move the address + * pointer forward or backward so code and data land in correct + * region. Remember to align the memory, and be sure to also emit the * section to ">ram :ram_phdr" or ">ucram :ucram_phdr" as * appropriate. (Forgetting the correct PHDR will actually work, as * the output tooling ignores it, but it will cause the linker to emit * 512MB of unused data into the output file!) * */ -#define SEGSTART_CACHED (ALIGN(64) | 0x20000000) -#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000) +#define UNCACHED_RAM_OFFSET 0x20000000 MEMORY { @@ -115,7 +115,7 @@ MEMORY org = RAM_BASE, len = RAM_SIZE ucram : - org = RAM_BASE - 0x20000000, + org = RAM_BASE - UNCACHED_RAM_OFFSET, len = RAM_SIZE #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST : @@ -421,13 +421,20 @@ SECTIONS KEEP (*(.fw_ready_metadata)) } >ram :ram_phdr - .noinit SEGSTART_UNCACHED : ALIGN(4) + /* + * Address pointer here is at cached ram. + * So need to go into uncached memory region, hence + * the subtraction. + */ + segstart_uncached_noinit = ALIGN(64) - UNCACHED_RAM_OFFSET; + + .noinit segstart_uncached_noinit : ALIGN(64) { *(.noinit) *(.noinit.*) } >ucram :ucram_phdr - .data SEGSTART_UNCACHED : ALIGN(4) + .data : ALIGN(64) { _data_start = ABSOLUTE(.); *(.data) @@ -448,7 +455,10 @@ SECTIONS . = ALIGN(4096); } >ucram :ucram_phdr - .lit4 SEGSTART_CACHED : ALIGN(4) + /* Going back into cached memory region. */ + segstart_cached_lit4 = ALIGN(64) + UNCACHED_RAM_OFFSET; + + .lit4 segstart_cached_lit4 : ALIGN(64) { _lit4_start = ABSOLUTE(.); *(*.lit4) @@ -462,8 +472,6 @@ SECTIONS * wants to use the cache */ - . = SEGSTART_UNCACHED; - #undef RAMABLE_REGION #undef ROMABLE_REGION #define RAMABLE_REGION ucram :ucram_phdr @@ -471,22 +479,28 @@ SECTIONS #include + /* Going back into cached memory region. */ + segstart_cached_cached = ALIGN(64) + UNCACHED_RAM_OFFSET; + /* This section is cached. By default it contains only declared * thread stacks, but applications can put symbols here too. */ - .cached SEGSTART_CACHED : + .cached segstart_cached_cached : { *(.cached .cached.*) } >ram :ram_phdr - .tm_clone_table SEGSTART_UNCACHED : + /* Going back into un-cached memory region. */ + segstart_uncached_tm_clone_table = ALIGN(64) - UNCACHED_RAM_OFFSET; + + .tm_clone_table segstart_uncached_tm_clone_table : { *(.tm_clone_table) } >ram :ram_phdr . = ALIGN(4096); - .bss SEGSTART_UNCACHED (NOLOAD) : + .bss ALIGN(64) (NOLOAD) : { _bss_start = ABSOLUTE(.); *(.dynsbss) @@ -506,15 +520,16 @@ SECTIONS _bss_end = ABSOLUTE(.); } >ucram :ucram_phdr - . = SEGSTART_UNCACHED; - _end = ALIGN(8); + _end = ALIGN(64); PROVIDE(end = ALIGN(8)); /* Re-adjust to the upper mapping for the final symbols below */ - . = SEGSTART_CACHED; + segstart_cached_stack = _end + UNCACHED_RAM_OFFSET; + . = segstart_cached_stack; __stack = L2_SRAM_BASE + L2_SRAM_SIZE; - . = SEGSTART_UNCACHED; + segstart_uncached_lpbuf = ALIGN(4) - UNCACHED_RAM_OFFSET; + . = segstart_uncached_lpbuf; /* dma buffers */ .lpbuf (NOLOAD): ALIGN(4) @@ -525,8 +540,7 @@ SECTIONS } >LP_SRAM_REGION . = L2_SRAM_BASE + L2_SRAM_SIZE; - . = SEGSTART_UNCACHED; - _heap_sentry = .; + _heap_sentry = . - UNCACHED_RAM_OFFSET; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } diff --git a/soc/xtensa/intel_adsp/cavs_v25/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld index 2cc7db55508..01516d2d8e8 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v25/linker.ld @@ -35,16 +35,16 @@ PROVIDE(_MemErrorHandler = 0x00000000); * data (e.g. stacks) or shared data that is managed with explicit * cache flush/invalidate operations. * - * These macros will set up a segment start address correctly, - * including alignment to a cache line. Be sure to also emit the + * The UNCACHED_RAM_OFFSET will be used before to move the address + * pointer forward or backward so code and data land in correct + * region. Remember to align the memory, and be sure to also emit the * section to ">ram :ram_phdr" or ">ucram :ucram_phdr" as * appropriate. (Forgetting the correct PHDR will actually work, as * the output tooling ignores it, but it will cause the linker to emit * 512MB of unused data into the output file!) * */ -#define SEGSTART_CACHED (ALIGN(64) | 0x20000000) -#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000) +#define UNCACHED_RAM_OFFSET 0x20000000 MEMORY { @@ -115,7 +115,7 @@ MEMORY org = RAM_BASE, len = RAM_SIZE ucram : - org = RAM_BASE - 0x20000000, + org = RAM_BASE - UNCACHED_RAM_OFFSET, len = RAM_SIZE #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST : @@ -465,13 +465,20 @@ SECTIONS KEEP (*(.fw_ready_metadata)) } >ram :ram_phdr - .noinit SEGSTART_UNCACHED : ALIGN(4) + /* + * Address pointer here is at cached ram. + * So need to go into uncached memory region, hence + * the subtraction. + */ + segstart_uncached_noinit = ALIGN(64) - UNCACHED_RAM_OFFSET; + + .noinit segstart_uncached_noinit : ALIGN(64) { *(.noinit) *(.noinit.*) } >ucram :ucram_phdr - .data SEGSTART_UNCACHED : ALIGN(4) + .data : ALIGN(64) { _data_start = ABSOLUTE(.); *(.data) @@ -492,7 +499,10 @@ SECTIONS . = ALIGN(4096); } >ucram :ucram_phdr - .lit4 SEGSTART_CACHED : ALIGN(4) + /* Going back into cached memory region. */ + segstart_cached_lit4 = ALIGN(64) + UNCACHED_RAM_OFFSET; + + .lit4 segstart_cached_lit4 : ALIGN(64) { _lit4_start = ABSOLUTE(.); *(*.lit4) @@ -505,7 +515,6 @@ SECTIONS * sections need to be linked in safe/uncached memory but common-rom * wants to use the cache */ - . = SEGSTART_UNCACHED; #undef RAMABLE_REGION #undef ROMABLE_REGION @@ -514,7 +523,9 @@ SECTIONS #include - .AltBootManifest SEGSTART_CACHED : ALIGN(8) + segstart_cached_altboot = ALIGN(64) + UNCACHED_RAM_OFFSET; + + .AltBootManifest segstart_cached_altboot : ALIGN(64) { /* Single entry of strorage manifest * consist of 3 items. Entries array @@ -546,14 +557,15 @@ SECTIONS /* This section is cached. By default it contains only declared * thread stacks, but applications can put symbols here too. */ - .cached SEGSTART_CACHED : + .cached : ALIGN(64) { *(.cached .cached.*) } >ram :ram_phdr - . = ALIGN(4096); + /* ...into uncached memory region. */ + segstart_uncached_bss = ALIGN(4096) - UNCACHED_RAM_OFFSET; - .bss SEGSTART_UNCACHED (NOLOAD) : + .bss segstart_uncached_bss (NOLOAD) : ALIGN(64) { _bss_start = ABSOLUTE(.); *(.dynsbss) @@ -573,15 +585,16 @@ SECTIONS _bss_end = ABSOLUTE(.); } >ucram :ucram_phdr - . = SEGSTART_UNCACHED; - _end = ALIGN(8); + _end = ALIGN(64); PROVIDE(end = ALIGN(8)); /* Re-adjust to the upper mapping for the final symbols below */ - . = SEGSTART_CACHED; + segstart_cached_stack = _end + UNCACHED_RAM_OFFSET; + . = segstart_cached_stack; __stack = L2_SRAM_BASE + L2_SRAM_SIZE; - . = SEGSTART_UNCACHED; + segstart_uncached_lpbuf = ALIGN(4) - UNCACHED_RAM_OFFSET; + . = segstart_uncached_lpbuf; /* dma buffers */ .lpbuf (NOLOAD): ALIGN(4) @@ -592,8 +605,7 @@ SECTIONS } >LP_SRAM_REGION . = L2_SRAM_BASE + L2_SRAM_SIZE; - . = SEGSTART_UNCACHED; - _heap_sentry = .; + _heap_sentry = . - UNCACHED_RAM_OFFSET; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) }