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arch/riscv: add Zaamo and Zlrsc extension subsets

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The Zaamo and Zalrsc Extension (Version v1.0.0, 2024-04-25; Ratified) split
the standard A extension into two subextensions. As of date, the `_zaamo`
and `_zlrsc` extension specifications are accepted by the upstream
in-development GCC through the `march` argument. This means that those
subextensions are not yet supported by GCC shipped with Zephyr SDK.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski 2025-01-15 11:44:10 +01:00 • committed by Benjamin Cabé
commit ee07eba569
2 changed files with 29 additions and 1 deletions
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16
arch/riscv/Kconfig.isa
View file

@ -33,6 +33,8 @@ config RISCV_ISA_EXT_M
config RISCV_ISA_EXT_A
bool
imply RISCV_ISA_EXT_ZAAMO
imply RISCV_ISA_EXT_ZLRSC
help
(A) - Standard Extension for Atomic Instructions
@ -111,6 +113,20 @@ config RISCV_ISA_EXT_ZIFENCEI
provides explicit synchronization between writes to instruction
memory and instruction fetches on the same hart.
config RISCV_ISA_EXT_ZAAMO
bool
help
(Zaamo) - Atomic memory operation subset of the A extension
The Zaamo extension enables support for AMO*.W/D-style instructions.
config RISCV_ISA_EXT_ZLRSC
bool
help
(Zlrsc) - Load-Reserved/Store-Conditional subset of the A extension
The Zlrsc extension enables support for LR.W/D and SC.W/D-style instructions.
config RISCV_ISA_EXT_ZBA
bool
help

14
cmake/compiler/gcc/target_riscv.cmake
View file

@ -53,6 +53,18 @@ if(CONFIG_RISCV_ISA_EXT_ZIFENCEI)
string(CONCAT riscv_march ${riscv_march} "_zifencei")
endif()
# Check whether we already imply Zaamo/Zlrsc by selecting the A extension; if not - check them
# individually and enable them as needed
if(NOT CONFIG_RISCV_ISA_EXT_A)
if(CONFIG_RISCV_ISA_EXT_ZAAMO)
string(CONCAT riscv_march ${riscv_march} "_zaamo")
endif()
if(CONFIG_RISCV_ISA_EXT_ZLRSC)
string(CONCAT riscv_march ${riscv_march} "_zlrsc")
endif()
endif()
if(CONFIG_RISCV_ISA_EXT_ZBA)
string(CONCAT riscv_march ${riscv_march} "_zba")
endif()
@ -90,4 +102,4 @@ set(LLEXT_APPEND_FLAGS
-mabi=${riscv_mabi}
-march=${riscv_march}
-mno-relax
)
)