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arch: arm: be able to infer Z_ARCH_EXCEPT() for baseline SOCs

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This commit makes it possible to infer Z_ARCH_EXCEPT()
calls in SVCs that escalate to HardFault due to being
invoked from priority level equal or higher to the
interrupt priority level of the SVC Handler.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos 2019-08-27 17:31:38 +02:00
commit eddf058e1e
1 changed files with 24 additions and 0 deletions
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24
arch/arm/core/cortex_m/fault.c
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@ -609,6 +609,30 @@ static u32_t HardFault(z_arch_esf_t *esf, bool *recoverable)
PR_FAULT_INFO("***** HARD FAULT *****");
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
/* Workaround for #18712:
* HardFault may be due to escalation, as a result of
* an SVC instruction that could not be executed; this
* can occur if Z_ARCH_EXCEPT() is called by an ISR,
* which executes at priority equal to the SVC handler
* priority. We handle the case of Kernel OOPS and Stack
* Fail here.
*/
u16_t *ret_addr = (u16_t *)esf->basic.pc;
/* SVC is a 16-bit instruction. On a synchronous SVC
* escalated to Hard Fault, the return address is the
* next instruction, i.e. after the SVC.
*/
#define _SVC_OPCODE 0xDF00
u16_t fault_insn = *(ret_addr - 1);
if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) {
PR_EXC("Z_ARCH_EXCEPT with reason %x\n", esf->basic.r0);
reason = esf->basic.r0;
}
#undef _SVC_OPCODE
*recoverable = memory_fault_recoverable(esf);
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
*recoverable = false;