soc: arm: kv5x: add NXP Kinetis KV5x SoC series support
Add initial support for the NXP Kinetis KV5x SoC series (MKV56F24 and MKV58F24). Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
This commit is contained in:
Filip Brozovic
Kumar Gala
parent
c07827f2d8
commit
edcb7deb88
21 changed files with 1075 additions and 0 deletions
7
dts/arm/nxp/nxp_kv56f1m0vlx24.dtsi
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7
dts/arm/nxp/nxp_kv56f1m0vlx24.dtsi
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/*
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* Copyright (c) 2019 SEAL AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_kv5xf1m0vlx24.dtsi>
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7
dts/arm/nxp/nxp_kv56f512vlx24.dtsi
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7
dts/arm/nxp/nxp_kv56f512vlx24.dtsi
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/*
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* Copyright (c) 2019 SEAL AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_kv5xf512vlx24.dtsi>
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7
dts/arm/nxp/nxp_kv58f1m0vlx24.dtsi
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7
dts/arm/nxp/nxp_kv58f1m0vlx24.dtsi
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/*
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* Copyright (c) 2019 SEAL AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_kv5xf1m0vlx24.dtsi>
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7
dts/arm/nxp/nxp_kv58f512vlx24.dtsi
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7
dts/arm/nxp/nxp_kv58f512vlx24.dtsi
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@ -0,0 +1,7 @@
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/*
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* Copyright (c) 2019 SEAL AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_kv5xf512vlx24.dtsi>
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330
dts/arm/nxp/nxp_kv5x.dtsi
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330
dts/arm/nxp/nxp_kv5x.dtsi
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@ -0,0 +1,330 @@
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/*
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* Copyright (c) 2019 SEAL AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/clock/kinetis_sim.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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/ {
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aliases {
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adc-0 = &adc0;
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gpio-a = &gpioa;
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gpio-b = &gpiob;
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gpio-c = &gpioc;
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gpio-d = &gpiod;
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gpio-e = &gpioe;
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i2c-0 = &i2c0;
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i2c-1 = &i2c1;
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pinmux-a = &pinmux_a;
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pinmux-b = &pinmux_b;
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pinmux-c = &pinmux_c;
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pinmux-d = &pinmux_d;
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pinmux-e = &pinmux_e;
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pwm-1 = &pwm1;
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pwm-2 = &pwm2;
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pwm-3 = &pwm3;
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pwm-4 = &pwm4;
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spi-0 = &spi0;
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spi-1 = &spi1;
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spi-2 = &spi2;
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uart-0 = &uart0;
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uart-1 = &uart1;
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uart-2 = &uart2;
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uart-3 = &uart3;
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uart-4 = &uart4;
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uart-5 = &uart5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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};
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};
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soc {
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mpu: mpu@4000d000 {
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compatible = "nxp,kinetis-mpu";
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reg = <0x4000d000 0x1000>;
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status = "disabled";
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};
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sim: sim@40047000 {
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compatible = "nxp,kinetis-sim";
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reg = <0x40047000 0x2000>;
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label = "SIM";
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#clock-cells = <3>;
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};
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mcg: clock-controller@40064000 {
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compatible = "nxp,kv58-mcg";
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reg = <0x40064000 0x1000>;
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system-clock-frequency = <240000000>;
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};
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osc: clock-controller@40065000 {
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compatible = "nxp,kv58-osc";
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reg = <0x40065000 0x4>;
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enable-external-reference;
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};
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flash_controller: flash-controller@40020000 {
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compatible = "nxp,kinetis-ftfe";
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label = "FLASH_CTRL";
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reg = <0x40020000 0x1000>;
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interrupts = <18 0>, <19 0>;
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interrupt-names = "command-complete", "read-collision";
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#address-cells = <1>;
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#size-cells = <1>;
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};
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adc0: adc@4003b000 {
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compatible = "nxp,kinetis-adc16";
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reg = <0x4003b000 0x1000>;
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interrupts = <37 0>;
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label = "ADC_0";
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status = "disabled";
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};
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gpioa: gpio@400ff000 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff000 0x40>;
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interrupts = <59 2>;
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label = "GPIO_0";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiob: gpio@400ff040 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff040 0x40>;
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interrupts = <60 2>;
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label = "GPIO_1";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioc: gpio@400ff080 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff080 0x40>;
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interrupts = <61 2>;
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label = "GPIO_2";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiod: gpio@400ff0c0 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff0c0 0x40>;
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interrupts = <62 2>;
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label = "GPIO_3";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioe: gpio@400ff100 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff100 0x40>;
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interrupts = <63 2>;
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label = "GPIO_4";
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gpio-controller;
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#gpio-cells = <2>;
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};
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i2c0: i2c@40066000 {
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compatible = "nxp,kinetis-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40066000 0x1000>;
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interrupts = <24 0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
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label = "I2C_0";
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status = "disabled";
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};
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i2c1: i2c@40067000 {
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compatible = "nxp,kinetis-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40067000 0x1000>;
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interrupts = <25 0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
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label = "I2C_1";
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status = "disabled";
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};
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pinmux_a: pinmux@40049000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x40049000 0x1000>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
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};
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pinmux_b: pinmux@4004a000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004a000 0x1000>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
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};
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pinmux_c: pinmux@4004b000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004b000 0x1000>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
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};
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pinmux_d: pinmux@4004c000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004c000 0x1000>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
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};
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pinmux_e: pinmux@4004d000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004d000 0x1000>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
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};
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pwm1: pwm@40038000 {
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compatible = "nxp,kinetis-ftm";
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reg = <0x40038000 0x1000>;
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interrupts = <42 0>;
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label = "FTM_0";
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status = "disabled";
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#pwm-cells = <2>;
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};
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pwm2: pwm@40039000 {
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compatible = "nxp,kinetis-ftm";
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reg = <0x40039000 0x1000>;
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interrupts = <43 0>;
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label = "FTM_1";
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status = "disabled";
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#pwm-cells = <2>;
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};
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pwm3: pwm@4003a000 {
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compatible = "nxp,kinetis-ftm";
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reg = <0x4003a000 0x1000>;
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interrupts = <53 0>;
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label = "FTM_2";
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status = "disabled";
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#pwm-cells = <2>;
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};
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pwm4: pwm@40026000 {
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compatible = "nxp,kinetis-ftm";
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reg = <0x40026000 0x1000>;
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interrupts = <71 0>;
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label = "FTM_3";
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status = "disabled";
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#pwm-cells = <2>;
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};
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spi0: spi@4002c000 {
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compatible = "nxp,kinetis-dspi";
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reg = <0x4002c000 0x1000>;
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interrupts = <26 3>;
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label = "SPI_0";
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status = "disabled";
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clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x103c 12>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@4002d000 {
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compatible = "nxp,kinetis-dspi";
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reg = <0x4002d000 0x1000>;
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interrupts = <27 3>;
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label = "SPI_1";
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status = "disabled";
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clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x103c 13>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi2: spi@400ac000 {
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compatible = "nxp,kinetis-dspi";
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reg = <0x400ac000 0x1000>;
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interrupts = <65 3>;
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label = "SPI_2";
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status = "disabled";
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clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1030 12>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: uart@4006a000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x4006a000 0x1000>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1034 10>;
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label = "UART_0";
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status = "disabled";
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};
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uart1: uart@4006b000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x4006b000 0x1000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1034 11>;
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label = "UART_1";
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status = "disabled";
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};
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uart2: uart@4006c000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x4006c000 0x1000>;
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interrupts = <35 0>, <36 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1034 12>;
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label = "UART_2";
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status = "disabled";
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};
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uart3: uart@4006d000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x4006d000 0x1000>;
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interrupts = <44 0>, <45 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1034 13>;
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label = "UART_3";
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status = "disabled";
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};
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uart4: uart@400ea000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x400ea000 0x1000>;
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interrupts = <46 0>, <47 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1028 10>;
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label = "UART_4";
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status = "disabled";
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};
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uart5: uart@400eb000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x400eb000 0x1000>;
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interrupts = <28 0>, <29 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1028 11>;
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label = "UART_5";
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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27
dts/arm/nxp/nxp_kv5xf1m0vlx24.dtsi
Normal file
27
dts/arm/nxp/nxp_kv5xf1m0vlx24.dtsi
Normal file
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/*
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* Copyright (c) 2019 SEAL AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <nxp/nxp_kv5x.dtsi>
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/ {
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/* 64KB ITCM @ 0, 128KB DTCM @ 20000000, 64KB OCRAM @ 2F000000 */
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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};
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&flash_controller {
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flash0: flash@10000000 {
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compatible = "soc-nv-flash";
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label = "MCUX_FLASH";
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reg = <0x10000000 DT_SIZE_K(1024)>;
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erase-block-size = <DT_SIZE_K(8)>;
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write-block-size = <8>;
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};
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};
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27
dts/arm/nxp/nxp_kv5xf512vlx24.dtsi
Normal file
27
dts/arm/nxp/nxp_kv5xf512vlx24.dtsi
Normal file
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/*
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* Copyright (c) 2019 SEAL AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <nxp/nxp_kv5x.dtsi>
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/ {
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/* 64KB ITCM @ 0, 64KB DTCM @ 20000000 */
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(64)>;
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};
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};
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&flash_controller {
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flash0: flash@10000000 {
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compatible = "soc-nv-flash";
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label = "MCUX_FLASH";
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reg = <0x10000000 DT_SIZE_K(512)>;
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erase-block-size = <DT_SIZE_K(8)>;
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write-block-size = <8>;
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};
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};
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@ -21,6 +21,7 @@ config SOC_PART_NUMBER
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default SOC_PART_NUMBER_KINETIS_KWX if SOC_SERIES_KINETIS_KWX
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default SOC_PART_NUMBER_KINETIS_KL2X if SOC_SERIES_KINETIS_KL2X
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default SOC_PART_NUMBER_KINETIS_KE1XF if SOC_SERIES_KINETIS_KE1XF
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default SOC_PART_NUMBER_KINETIS_KV5X if SOC_SERIES_KINETIS_KV5X
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config HAS_OSC
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bool
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10
soc/arm/nxp_kinetis/kv5x/CMakeLists.txt
Normal file
10
soc/arm/nxp_kinetis/kv5x/CMakeLists.txt
Normal file
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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soc.c
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wdog.S
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)
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zephyr_sources_ifdef(
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CONFIG_ARM_MPU
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arm_mpu_regions.c
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)
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11
soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv56f24
Normal file
11
soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv56f24
Normal file
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@ -0,0 +1,11 @@
|
|||
# Kinetis KV56F24 configuration options
|
||||
|
||||
# Copyright (c) 2019 SEAL AG
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MKV56F24
|
||||
|
||||
config SOC
|
||||
default "mkv56f24"
|
||||
|
||||
endif # SOC_MKV56F24
|
||||
11
soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv58f24
Normal file
11
soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv58f24
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Kinetis KV58F24 configuration options
|
||||
|
||||
# Copyright (c) 2019 SEAL AG
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_MKV58F24
|
||||
|
||||
config SOC
|
||||
default "mkv58f24"
|
||||
|
||||
endif # SOC_MKV58F24
|
||||
83
soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.series
Normal file
83
soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.series
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
# Kinetis KV5x series configuration options
|
||||
|
||||
# Copyright (c) 2019 SEAL AG
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_KINETIS_KV5X
|
||||
|
||||
config SOC_SERIES
|
||||
default "kv5x"
|
||||
|
||||
config NUM_IRQS
|
||||
# must be >= the highest interrupt number used
|
||||
default 121
|
||||
|
||||
if ADC
|
||||
|
||||
config ADC_MCUX_ADC16
|
||||
default y
|
||||
|
||||
endif # ADC
|
||||
|
||||
if CLOCK_CONTROL
|
||||
|
||||
config CLOCK_CONTROL_MCUX_SIM
|
||||
default y
|
||||
|
||||
endif # CLOCK_CONTROL
|
||||
|
||||
if FLASH
|
||||
|
||||
config SOC_FLASH_MCUX
|
||||
default y
|
||||
|
||||
endif # FLASH
|
||||
|
||||
config GPIO
|
||||
default y
|
||||
|
||||
if GPIO
|
||||
|
||||
config GPIO_MCUX
|
||||
default y
|
||||
|
||||
endif # GPIO
|
||||
|
||||
if I2C
|
||||
|
||||
config I2C_MCUX
|
||||
default y
|
||||
|
||||
endif # I2C
|
||||
|
||||
if PINMUX
|
||||
|
||||
config PINMUX_MCUX
|
||||
default y
|
||||
|
||||
endif # PINMUX
|
||||
|
||||
if PWM
|
||||
|
||||
config PWM_MCUX_FTM
|
||||
default y
|
||||
|
||||
endif # PWM
|
||||
|
||||
if SERIAL
|
||||
|
||||
config UART_MCUX
|
||||
default y
|
||||
|
||||
endif # SERIAL
|
||||
|
||||
if SPI
|
||||
|
||||
config SPI_MCUX_DSPI
|
||||
default y
|
||||
|
||||
endif # SPI
|
||||
|
||||
source "soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv*"
|
||||
|
||||
endif # SOC_SERIES_KINETIS_KV5X
|
||||
23
soc/arm/nxp_kinetis/kv5x/Kconfig.series
Normal file
23
soc/arm/nxp_kinetis/kv5x/Kconfig.series
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
# Kconfig - Kinetis KV5x series MCU
|
||||
#
|
||||
# Copyright (c) 2019 SEAL AG
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
config SOC_SERIES_KINETIS_KV5X
|
||||
bool "Kinetis KV5x Series MCU"
|
||||
select CPU_CORTEX_M7
|
||||
select SOC_FAMILY_KINETIS
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_FPU
|
||||
select CLOCK_CONTROL
|
||||
select HAS_MCUX
|
||||
select HAS_MCUX_ADC16
|
||||
select HAS_MCUX_FTFX
|
||||
select HAS_MCUX_FTM
|
||||
select HAS_MCUX_SIM
|
||||
select HAS_OSC
|
||||
select HAS_MCG
|
||||
help
|
||||
Enable support for Kinetis KV5x MCU series
|
||||
96
soc/arm/nxp_kinetis/kv5x/Kconfig.soc
Normal file
96
soc/arm/nxp_kinetis/kv5x/Kconfig.soc
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
# Kinetis KV5x series MCU
|
||||
|
||||
# Copyright (c) 2019 SEAL AG
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
choice
|
||||
prompt "Kinetis KV5x MCU Selection"
|
||||
depends on SOC_SERIES_KINETIS_KV5X
|
||||
|
||||
config SOC_MKV56F24
|
||||
bool "MKV56F24"
|
||||
|
||||
config SOC_MKV58F24
|
||||
bool "MKV58F24"
|
||||
|
||||
endchoice
|
||||
|
||||
if SOC_SERIES_KINETIS_KV5X
|
||||
|
||||
config SOC_PART_NUMBER_MKV56F512VLL24
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MKV56F512VLQ24
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MKV56F1M0VLL24
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MKV56F1M0VLQ24
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MKV58F512VLL24
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MKV58F512VLQ24
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MKV58F1M0VLL24
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_MKV58F1M0VLQ24
|
||||
bool
|
||||
|
||||
config SOC_PART_NUMBER_KINETIS_KV5X
|
||||
string
|
||||
default "MKV56F512VLL24" if SOC_PART_NUMBER_MKV56F512VLL24
|
||||
default "MKV56F512VLQ24" if SOC_PART_NUMBER_MKV56F512VLQ24
|
||||
default "MKV56F1M0VLL24" if SOC_PART_NUMBER_MKV56F1M0VLL24
|
||||
default "MKV56F1M0VLQ24" if SOC_PART_NUMBER_MKV56F1M0VLQ24
|
||||
default "MKV58F512VLL24" if SOC_PART_NUMBER_MKV58F512VLL24
|
||||
default "MKV58F512VLQ24" if SOC_PART_NUMBER_MKV58F512VLQ24
|
||||
default "MKV58F1M0VLL24" if SOC_PART_NUMBER_MKV58F1M0VLL24
|
||||
default "MKV58F1M0VLQ24" if SOC_PART_NUMBER_MKV58F1M0VLQ24
|
||||
help
|
||||
This string holds the full part number of the SoC. It is a
|
||||
hidden option that you should not set directly. The part
|
||||
number selection choice defines the default value for this
|
||||
string.
|
||||
|
||||
config KV5X_CORE_CLOCK_DIVIDER
|
||||
int "Freescale KV5x core clock divider"
|
||||
default 1
|
||||
help
|
||||
This option specifies the divide value for the KV5X processor core clock
|
||||
from the system clock.
|
||||
|
||||
config KV5X_BUS_CLOCK_DIVIDER
|
||||
int "Freescale KV5x bus clock divider"
|
||||
default 2
|
||||
help
|
||||
This option specifies the divide value for the KV5X bus clock from the
|
||||
system clock.
|
||||
|
||||
config KV5X_FLEXBUS_CLOCK_DIVIDER
|
||||
int "Freescale KV5x FlexBus clock divider"
|
||||
default 4
|
||||
help
|
||||
This option specifies the divide value for the KV5X FlexBus clock from the
|
||||
system clock.
|
||||
|
||||
config KV5X_FLASH_CLOCK_DIVIDER
|
||||
int "Freescale KV5x flash clock divider"
|
||||
default 10
|
||||
help
|
||||
This option specifies the divide value for the KV5X flash clock from the
|
||||
system clock.
|
||||
|
||||
config WDOG_INIT
|
||||
def_bool y
|
||||
help
|
||||
This processor enables the watchdog timer with a short
|
||||
window for configuration upon reset. Therefore, this
|
||||
requires that the watchdog be configured during reset
|
||||
handling.
|
||||
|
||||
endif # SOC_SERIES_KINETIS_KV5X
|
||||
30
soc/arm/nxp_kinetis/kv5x/arm_mpu_mem_cfg.h
Normal file
30
soc/arm/nxp_kinetis/kv5x/arm_mpu_mem_cfg.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Linaro Limited.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _ARM_MPU_MEM_CFG_H_
|
||||
#define _ARM_MPU_MEM_CFG_H_
|
||||
|
||||
#include <soc.h>
|
||||
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
|
||||
|
||||
/* Flash Region Definitions */
|
||||
#if CONFIG_FLASH_SIZE == 512
|
||||
#define REGION_FLASH_SIZE REGION_512K
|
||||
#elif CONFIG_FLASH_SIZE == 1024
|
||||
#define REGION_FLASH_SIZE REGION_1M
|
||||
#else
|
||||
#error "Unsupported configuration"
|
||||
#endif
|
||||
|
||||
/* SRAM Region Definitions */
|
||||
#if CONFIG_SRAM_SIZE == 64
|
||||
#define REGION_SRAM_0_SIZE REGION_64K
|
||||
#elif CONFIG_SRAM_SIZE == 128
|
||||
#define REGION_SRAM_0_SIZE REGION_128K
|
||||
#else
|
||||
#error "Unsupported configuration"
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_MPU_MEM_CFG_H_ */
|
||||
26
soc/arm/nxp_kinetis/kv5x/arm_mpu_regions.c
Normal file
26
soc/arm/nxp_kinetis/kv5x/arm_mpu_regions.c
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Linaro Limited.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
|
||||
|
||||
#include "arm_mpu_mem_cfg.h"
|
||||
|
||||
static const struct arm_mpu_region mpu_regions[] = {
|
||||
/* Region 0 */
|
||||
MPU_REGION_ENTRY("FLASH_0",
|
||||
CONFIG_FLASH_BASE_ADDRESS,
|
||||
REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
|
||||
/* Region 1 */
|
||||
MPU_REGION_ENTRY("SRAM_0",
|
||||
CONFIG_SRAM_BASE_ADDRESS,
|
||||
REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
|
||||
};
|
||||
|
||||
const struct arm_mpu_config mpu_config = {
|
||||
.num_regions = ARRAY_SIZE(mpu_regions),
|
||||
.mpu_regions = mpu_regions,
|
||||
};
|
||||
137
soc/arm/nxp_kinetis/kv5x/dts_fixup.h
Normal file
137
soc/arm/nxp_kinetis/kv5x/dts_fixup.h
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* Copyright (c) 2019 SEAL AG
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* SoC level DTS fixup file */
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_SIM_NAME DT_NXP_KINETIS_SIM_40047000_LABEL
|
||||
#ifdef DT_NXP_KINETIS_SIM_40047000_CLKOUT_DIVIDER
|
||||
#define DT_SIM_CLKOUT_DIVIDER DT_NXP_KINETIS_SIM_40047000_CLKOUT_DIVIDER
|
||||
#endif /* DT_NXP_KINETIS_SIM_40047000_CLKOUT_DIVIDER */
|
||||
#ifdef DT_NXP_KINETIS_SIM_40047000_CLKOUT_SOURCE
|
||||
#define DT_SIM_CLKOUT_SOURCE DT_NXP_KINETIS_SIM_40047000_CLKOUT_SOURCE
|
||||
#endif /* DT_NXP_KINETIS_SIM_40047000_CLKOUT_SOURCE */
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFE_40020000_BASE_ADDRESS
|
||||
#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFE_40020000_LABEL
|
||||
|
||||
#define DT_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS
|
||||
#define DT_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0
|
||||
#define DT_ADC_0_IRQ_PRI DT_NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY
|
||||
#define DT_ADC_0_NAME DT_NXP_KINETIS_ADC16_4003B000_LABEL
|
||||
|
||||
#define DT_FTM_1_BASE_ADDRESS DT_NXP_KINETIS_FTM_40038000_BASE_ADDRESS
|
||||
#define DT_FTM_1_IRQ DT_NXP_KINETIS_FTM_40038000_IRQ_0
|
||||
#define DT_FTM_1_IRQ_PRI DT_NXP_KINETIS_FTM_40038000_IRQ_0_PRIORITY
|
||||
#define DT_FTM_1_NAME DT_NXP_KINETIS_FTM_40038000_LABEL
|
||||
|
||||
#define DT_FTM_2_BASE_ADDRESS DT_NXP_KINETIS_FTM_40039000_BASE_ADDRESS
|
||||
#define DT_FTM_2_IRQ DT_NXP_KINETIS_FTM_40039000_IRQ_0
|
||||
#define DT_FTM_2_IRQ_PRI DT_NXP_KINETIS_FTM_40039000_IRQ_0_PRIORITY
|
||||
#define DT_FTM_2_NAME DT_NXP_KINETIS_FTM_40039000_LABEL
|
||||
|
||||
#define DT_FTM_3_BASE_ADDRESS DT_NXP_KINETIS_FTM_4003A000_BASE_ADDRESS
|
||||
#define DT_FTM_3_IRQ DT_NXP_KINETIS_FTM_4003A000_IRQ_0
|
||||
#define DT_FTM_3_IRQ_PRI DT_NXP_KINETIS_FTM_4003A000_IRQ_0_PRIORITY
|
||||
#define DT_FTM_3_NAME DT_NXP_KINETIS_FTM_4003A000_LABEL
|
||||
|
||||
#define DT_FTM_4_BASE_ADDRESS DT_NXP_KINETIS_FTM_40026000_BASE_ADDRESS
|
||||
#define DT_FTM_4_IRQ DT_NXP_KINETIS_FTM_40026000_IRQ_0
|
||||
#define DT_FTM_4_IRQ_PRI DT_NXP_KINETIS_FTM_40026000_IRQ_0_PRIORITY
|
||||
#define DT_FTM_4_NAME DT_NXP_KINETIS_FTM_40026000_LABEL
|
||||
|
||||
#define DT_I2C_0_NAME DT_NXP_KINETIS_I2C_40066000_LABEL
|
||||
#define DT_I2C_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_I2C_40066000_BASE_ADDRESS
|
||||
#define DT_I2C_MCUX_0_IRQ DT_NXP_KINETIS_I2C_40066000_IRQ_0
|
||||
#define DT_I2C_MCUX_0_IRQ_PRI DT_NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY
|
||||
#define DT_I2C_MCUX_0_BITRATE DT_NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY
|
||||
|
||||
#define DT_I2C_1_NAME DT_NXP_KINETIS_I2C_40067000_LABEL
|
||||
#define DT_I2C_MCUX_1_BASE_ADDRESS DT_NXP_KINETIS_I2C_40067000_BASE_ADDRESS
|
||||
#define DT_I2C_MCUX_1_IRQ DT_NXP_KINETIS_I2C_40067000_IRQ_0
|
||||
#define DT_I2C_MCUX_1_IRQ_PRI DT_NXP_KINETIS_I2C_40067000_IRQ_0_PRIORITY
|
||||
#define DT_I2C_MCUX_1_BITRATE DT_NXP_KINETIS_I2C_40067000_CLOCK_FREQUENCY
|
||||
|
||||
#define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
|
||||
#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
|
||||
#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
|
||||
#define DT_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
|
||||
#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
|
||||
|
||||
#define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
|
||||
#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
|
||||
#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
|
||||
#define DT_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER
|
||||
#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME
|
||||
|
||||
#define DT_SPI_2_NAME DT_NXP_KINETIS_DSPI_400AC000_LABEL
|
||||
#define DT_SPI_2_BASE_ADDRESS DT_NXP_KINETIS_DSPI_400AC000_BASE_ADDRESS
|
||||
#define DT_SPI_2_IRQ DT_NXP_KINETIS_DSPI_400AC000_IRQ_0
|
||||
#define DT_SPI_2_IRQ_PRI DT_NXP_KINETIS_DSPI_400AC000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_CLOCK_NAME DT_NXP_KINETIS_DSPI_400AC000_CLOCK_CONTROLLER
|
||||
#define DT_SPI_2_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_400AC000_CLOCK_NAME
|
||||
|
||||
#define DT_UART_MCUX_0_BAUD_RATE DT_NXP_KINETIS_UART_4006A000_CURRENT_SPEED
|
||||
#define DT_UART_MCUX_0_NAME DT_NXP_KINETIS_UART_4006A000_LABEL
|
||||
#define DT_UART_MCUX_0_IRQ_ERROR DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR
|
||||
#define DT_UART_MCUX_0_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR_PRIORITY
|
||||
#define DT_UART_MCUX_0_IRQ_STATUS DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS
|
||||
#define DT_UART_MCUX_0_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY
|
||||
#define DT_UART_MCUX_0_HW_FLOW_CONTROL DT_NXP_KINETIS_UART_4006A000_HW_FLOW_CONTROL
|
||||
#define DT_UART_MCUX_0_CLOCK_NAME DT_NXP_KINETIS_UART_4006A000_CLOCK_CONTROLLER
|
||||
#define DT_UART_MCUX_0_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006A000_CLOCK_NAME
|
||||
|
||||
#define DT_UART_MCUX_1_BAUD_RATE DT_NXP_KINETIS_UART_4006B000_CURRENT_SPEED
|
||||
#define DT_UART_MCUX_1_NAME DT_NXP_KINETIS_UART_4006B000_LABEL
|
||||
#define DT_UART_MCUX_1_IRQ_ERROR DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR
|
||||
#define DT_UART_MCUX_1_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR_PRIORITY
|
||||
#define DT_UART_MCUX_1_IRQ_STATUS DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS
|
||||
#define DT_UART_MCUX_1_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY
|
||||
#define DT_UART_MCUX_1_HW_FLOW_CONTROL DT_NXP_KINETIS_UART_4006B000_HW_FLOW_CONTROL
|
||||
#define DT_UART_MCUX_1_CLOCK_NAME DT_NXP_KINETIS_UART_4006B000_CLOCK_CONTROLLER
|
||||
#define DT_UART_MCUX_1_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006B000_CLOCK_NAME
|
||||
|
||||
#define DT_UART_MCUX_2_BAUD_RATE DT_NXP_KINETIS_UART_4006C000_CURRENT_SPEED
|
||||
#define DT_UART_MCUX_2_NAME DT_NXP_KINETIS_UART_4006C000_LABEL
|
||||
#define DT_UART_MCUX_2_IRQ_ERROR DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR
|
||||
#define DT_UART_MCUX_2_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR_PRIORITY
|
||||
#define DT_UART_MCUX_2_IRQ_STATUS DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS
|
||||
#define DT_UART_MCUX_2_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY
|
||||
#define DT_UART_MCUX_2_HW_FLOW_CONTROL DT_NXP_KINETIS_UART_4006C000_HW_FLOW_CONTROL
|
||||
#define DT_UART_MCUX_2_CLOCK_NAME DT_NXP_KINETIS_UART_4006C000_CLOCK_CONTROLLER
|
||||
#define DT_UART_MCUX_2_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006C000_CLOCK_NAME
|
||||
|
||||
#define DT_UART_MCUX_3_BAUD_RATE DT_NXP_KINETIS_UART_4006D000_CURRENT_SPEED
|
||||
#define DT_UART_MCUX_3_NAME DT_NXP_KINETIS_UART_4006D000_LABEL
|
||||
#define DT_UART_MCUX_3_IRQ_ERROR DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR
|
||||
#define DT_UART_MCUX_3_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR_PRIORITY
|
||||
#define DT_UART_MCUX_3_IRQ_STATUS DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS
|
||||
#define DT_UART_MCUX_3_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY
|
||||
#define DT_UART_MCUX_3_HW_FLOW_CONTROL DT_NXP_KINETIS_UART_4006D000_HW_FLOW_CONTROL
|
||||
#define DT_UART_MCUX_3_CLOCK_NAME DT_NXP_KINETIS_UART_4006D000_CLOCK_CONTROLLER
|
||||
#define DT_UART_MCUX_3_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006D000_CLOCK_NAME
|
||||
|
||||
#define DT_UART_MCUX_4_BAUD_RATE DT_NXP_KINETIS_UART_400EA000_CURRENT_SPEED
|
||||
#define DT_UART_MCUX_4_NAME DT_NXP_KINETIS_UART_400EA000_LABEL
|
||||
#define DT_UART_MCUX_4_IRQ_ERROR DT_NXP_KINETIS_UART_400EA000_IRQ_ERROR
|
||||
#define DT_UART_MCUX_4_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_400EA000_IRQ_ERROR_PRIORITY
|
||||
#define DT_UART_MCUX_4_IRQ_STATUS DT_NXP_KINETIS_UART_400EA000_IRQ_STATUS
|
||||
#define DT_UART_MCUX_4_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_400EA000_IRQ_STATUS_PRIORITY
|
||||
#define DT_UART_MCUX_4_HW_FLOW_CONTROL DT_NXP_KINETIS_UART_400EA000_HW_FLOW_CONTROL
|
||||
#define DT_UART_MCUX_4_CLOCK_NAME DT_NXP_KINETIS_UART_400EA000_CLOCK_CONTROLLER
|
||||
#define DT_UART_MCUX_4_CLOCK_SUBSYS DT_NXP_KINETIS_UART_400EA000_CLOCK_NAME
|
||||
|
||||
#define DT_UART_MCUX_5_BAUD_RATE DT_NXP_KINETIS_UART_400EB000_CURRENT_SPEED
|
||||
#define DT_UART_MCUX_5_NAME DT_NXP_KINETIS_UART_400EB000_LABEL
|
||||
#define DT_UART_MCUX_5_IRQ_ERROR DT_NXP_KINETIS_UART_400EB000_IRQ_ERROR
|
||||
#define DT_UART_MCUX_5_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_400EB000_IRQ_ERROR_PRIORITY
|
||||
#define DT_UART_MCUX_5_IRQ_STATUS DT_NXP_KINETIS_UART_400EB000_IRQ_STATUS
|
||||
#define DT_UART_MCUX_5_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_400EB000_IRQ_STATUS_PRIORITY
|
||||
#define DT_UART_MCUX_5_HW_FLOW_CONTROL DT_NXP_KINETIS_UART_400EB000_HW_FLOW_CONTROL
|
||||
#define DT_UART_MCUX_5_CLOCK_NAME DT_NXP_KINETIS_UART_400EB000_CLOCK_CONTROLLER
|
||||
#define DT_UART_MCUX_5_CLOCK_SUBSYS DT_NXP_KINETIS_UART_400EB000_CLOCK_NAME
|
||||
14
soc/arm/nxp_kinetis/kv5x/linker.ld
Normal file
14
soc/arm/nxp_kinetis/kv5x/linker.ld
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2014 Wind River Systems, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* This is the linker script for both standard images and XIP images.
|
||||
*/
|
||||
|
||||
#include <arch/arm/cortex_m/scripts/linker.ld>
|
||||
115
soc/arm/nxp_kinetis/kv5x/soc.c
Normal file
115
soc/arm/nxp_kinetis/kv5x/soc.c
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright (c) 2019 SEAL AG
|
||||
*
|
||||
* Based on NXP K6x soc.c, which is:
|
||||
* Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <kernel.h>
|
||||
#include <device.h>
|
||||
#include <init.h>
|
||||
#include <fsl_common.h>
|
||||
#include <fsl_clock.h>
|
||||
|
||||
#define PLLFLLSEL_MCGFLLCLK (0)
|
||||
#define PLLFLLSEL_MCGPLLCLK (1)
|
||||
#define PLLFLLSEL_IRC48MHZ (3)
|
||||
|
||||
#define ER32KSEL_OSC32KCLK (0)
|
||||
#define ER32KSEL_LPO1KHZ (3)
|
||||
|
||||
#define RUNM_RUN (0)
|
||||
#define RUNM_VLPR (2)
|
||||
#define RUNM_HSRUN (3)
|
||||
|
||||
static const osc_config_t osc_config = {
|
||||
.freq = CONFIG_OSC_XTAL0_FREQ,
|
||||
.capLoad = 0,
|
||||
|
||||
#if defined(CONFIG_OSC_EXTERNAL)
|
||||
.workMode = kOSC_ModeExt,
|
||||
#elif defined(CONFIG_OSC_LOW_POWER)
|
||||
.workMode = kOSC_ModeOscLowPower,
|
||||
#elif defined(CONFIG_OSC_HIGH_GAIN)
|
||||
.workMode = kOSC_ModeOscHighGain,
|
||||
#else
|
||||
#error "An oscillator mode must be defined"
|
||||
#endif
|
||||
|
||||
.oscerConfig = {
|
||||
.enableMode = kOSC_ErClkEnable,
|
||||
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
|
||||
FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
|
||||
.erclkDiv = 0U,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
static const mcg_pll_config_t pll0_config = {
|
||||
.enableMode = 0U,
|
||||
.prdiv = CONFIG_MCG_PRDIV0,
|
||||
.vdiv = CONFIG_MCG_VDIV0,
|
||||
};
|
||||
|
||||
static const sim_clock_config_t sim_config = {
|
||||
/* PLLFLLSEL: select PLL. */
|
||||
.pllFllSel = PLLFLLSEL_MCGPLLCLK,
|
||||
/* ERCLK32K selection: use system oscillator. */
|
||||
.er32kSrc = ER32KSEL_OSC32KCLK,
|
||||
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_KV5X_CORE_CLOCK_DIVIDER - 1) |
|
||||
SIM_CLKDIV1_OUTDIV2(CONFIG_KV5X_BUS_CLOCK_DIVIDER - 1) |
|
||||
SIM_CLKDIV1_OUTDIV3(CONFIG_KV5X_FLEXBUS_CLOCK_DIVIDER - 1) |
|
||||
SIM_CLKDIV1_OUTDIV4(CONFIG_KV5X_FLASH_CLOCK_DIVIDER - 1),
|
||||
};
|
||||
|
||||
static ALWAYS_INLINE void clk_init(void)
|
||||
{
|
||||
CLOCK_SetSimSafeDivs();
|
||||
|
||||
CLOCK_InitOsc0(&osc_config);
|
||||
CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
|
||||
|
||||
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0_config);
|
||||
|
||||
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
|
||||
CONFIG_MCG_FCRDIV);
|
||||
|
||||
CLOCK_SetSimConfig(&sim_config);
|
||||
}
|
||||
|
||||
static int kv5x_init(struct device *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
unsigned int old_level; /* old interrupt lock level */
|
||||
|
||||
/* Disable interrupts */
|
||||
old_level = irq_lock();
|
||||
|
||||
/* release I/O power hold to allow normal run state */
|
||||
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
|
||||
|
||||
/* Switch to HSRUN mode */
|
||||
SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK;
|
||||
SMC->PMCTRL = (SMC->PMCTRL & ~SMC_PMCTRL_RUNM_MASK) |
|
||||
SMC_PMCTRL_RUNM(RUNM_HSRUN);
|
||||
|
||||
/* Initialize system clocks and PLL */
|
||||
clk_init();
|
||||
|
||||
/*
|
||||
* Install default handler that simply resets the CPU if
|
||||
* configured in the kernel, NOP otherwise
|
||||
*/
|
||||
NMI_INIT();
|
||||
|
||||
/* Restore interrupt state */
|
||||
irq_unlock(old_level);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(kv5x_init, PRE_KERNEL_1, 0);
|
||||
32
soc/arm/nxp_kinetis/kv5x/soc.h
Normal file
32
soc/arm/nxp_kinetis/kv5x/soc.h
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2019 SEAL AG
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#include <sys/util.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <fsl_common.h>
|
||||
|
||||
/* Add include for DTS generated information */
|
||||
#include <generated_dts_board.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/* address bases */
|
||||
#define PERIPH_ADDR_BASE_WDOG 0x40052000 /* Watchdog Timer module */
|
||||
|
||||
#endif /* _SOC__H_ */
|
||||
74
soc/arm/nxp_kinetis/kv5x/wdog.S
Normal file
74
soc/arm/nxp_kinetis/kv5x/wdog.S
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* Copyright (c) 2014 Wind River Systems, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Watchdog initialization for kv5x platform
|
||||
*
|
||||
* This module initializes the watchdog for the kv5x platform.
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <toolchain.h>
|
||||
#include <linker/sections.h>
|
||||
|
||||
_ASM_FILE_PROLOGUE
|
||||
|
||||
GTEXT(z_arm_watchdog_init)
|
||||
|
||||
/* watchdog register offsets */
|
||||
#define WDOG_SCTRL_HI_OFFSET 0x0
|
||||
#define WDOG_UNLOCK_OFFSET 0xE
|
||||
|
||||
/* watchdog command words */
|
||||
#define WDOG_UNLOCK_1_CMD 0xC520
|
||||
#define WDOG_UNLOCK_2_CMD 0xD928
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Watchdog timer disable routine
|
||||
*
|
||||
* This routine will disable the watchdog timer.
|
||||
*
|
||||
* @return N/A
|
||||
*/
|
||||
|
||||
SECTION_FUNC(TEXT,z_arm_watchdog_init)
|
||||
/*
|
||||
* NOTE: DO NOT SINGLE STEP THROUGH THIS FUNCTION!!!
|
||||
* There are timing requirements for the execution of the unlock process.
|
||||
* Single stepping through the code will cause the CPU to reset.
|
||||
*/
|
||||
|
||||
/*
|
||||
* First unlock the watchdog so that we can write to registers.
|
||||
*
|
||||
* This sequence must execute within 20 clock cycles, so disable
|
||||
* interrupts to keep the code atomic and ensure the timing.
|
||||
*/
|
||||
|
||||
ldr r0, =PERIPH_ADDR_BASE_WDOG
|
||||
|
||||
movw r1, #WDOG_UNLOCK_1_CMD
|
||||
strh r1, [r0, #WDOG_UNLOCK_OFFSET]
|
||||
|
||||
movw r1, #WDOG_UNLOCK_2_CMD
|
||||
strh r1, [r0, #WDOG_UNLOCK_OFFSET]
|
||||
|
||||
/*
|
||||
* Disable the watchdog.
|
||||
*
|
||||
* Writes to control/configuration registers must execute within
|
||||
* 256 clock cycles after unlocking.
|
||||
*/
|
||||
|
||||
ldrh r1, [r0, #WDOG_SCTRL_HI_OFFSET]
|
||||
mov r2, #1
|
||||
bics r1, r2
|
||||
strh r1, [r0, #WDOG_SCTRL_HI_OFFSET]
|
||||
|
||||
bx lr
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue