From ed37374dacf428877acced1ebe3ffa8590396cca Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Wed, 23 Aug 2023 13:33:47 +0800 Subject: [PATCH] ITE: drivers/pwm: Add the flag of PWM output open-drain mode This flag is used when the PWM output is set to open-drain mode. Signed-off-by: Tim Lin --- drivers/pwm/pwm_ite_it8xxx2.c | 5 +++++ include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h | 10 ++++++++++ soc/riscv/riscv-ite/common/check_regs.c | 8 ++++++++ soc/riscv/riscv-ite/common/chip_chipregs.h | 4 ++++ 4 files changed, 27 insertions(+) diff --git a/drivers/pwm/pwm_ite_it8xxx2.c b/drivers/pwm/pwm_ite_it8xxx2.c index de7b769826e..61081550563 100644 --- a/drivers/pwm/pwm_ite_it8xxx2.c +++ b/drivers/pwm/pwm_ite_it8xxx2.c @@ -106,6 +106,11 @@ static int pwm_it8xxx2_set_cycles(const struct device *dev, *reg_pwmpol &= ~BIT(ch); } + /* Enable PWM output open-drain */ + if (flags & PWM_IT8XXX2_OPEN_DRAIN) { + inst->PWMODENR |= BIT(ch); + } + /* If pulse cycles is 0, set duty cycle 0 and enable pwm channel */ if (pulse_cycles == 0) { *reg_dcr = 0; diff --git a/include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h b/include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h index 0f2ba5b069f..19fd7a14d30 100644 --- a/include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h +++ b/include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h @@ -6,6 +6,8 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_ +#include + /* PWM prescaler references */ #define PWM_PRESCALER_C4 1 #define PWM_PRESCALER_C6 2 @@ -21,4 +23,12 @@ #define PWM_CHANNEL_6 6 #define PWM_CHANNEL_7 7 +/* + * Provides a type to hold PWM configuration flags. + * + * The upper 8 bits are reserved for SoC specific flags. + * Output onpe-drain flag [ 8 ] + */ +#define PWM_IT8XXX2_OPEN_DRAIN BIT(8) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_ */ diff --git a/soc/riscv/riscv-ite/common/check_regs.c b/soc/riscv/riscv-ite/common/check_regs.c index efa8a37a961..c655f850dac 100644 --- a/soc/riscv/riscv-ite/common/check_regs.c +++ b/soc/riscv/riscv-ite/common/check_regs.c @@ -232,3 +232,11 @@ IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_RXFRDRB1, 0x0d); IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_FTCB1R, 0x19); IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_HPR2, 0x1e); IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_RXVLISR, 0x27); + +/* PWM register structure check */ +IT8XXX2_REG_SIZE_CHECK(pwm_it8xxx2_regs, 0x4a); +IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, C0CPRS, 0x00); +IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, CTR1M, 0x10); +IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, C4CPRS, 0x27); +IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, CTR2, 0x42); +IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, PWMODENR, 0x49); diff --git a/soc/riscv/riscv-ite/common/chip_chipregs.h b/soc/riscv/riscv-ite/common/chip_chipregs.h index 78ac458e491..1fccd45853b 100644 --- a/soc/riscv/riscv-ite/common/chip_chipregs.h +++ b/soc/riscv/riscv-ite/common/chip_chipregs.h @@ -221,6 +221,10 @@ struct pwm_it8xxx2_regs { volatile uint8_t CTR2; /* 0x043: Cycle Time3 */ volatile uint8_t CTR3; + /* 0x044~0x048: Reserved7 */ + volatile uint8_t reserved7[5]; + /* 0x049: PWM Output Open-Drain Enable */ + volatile uint8_t PWMODENR; }; #endif /* !__ASSEMBLER__ */