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arch: xtensa: intel_s1000: Reference clock API

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Added a function to obtain the reference clock frequency value based on
SoC's bootstraps.
Added M/N divider base address in SoC header file

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
This commit is contained in:
Sathish Kuttan 2018-05-21 10:50:59 -07:00 • committed by Anas Nashif
commit ed33f43e48
2 changed files with 43 additions and 2 deletions
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31
arch/xtensa/soc/intel_s1000/soc.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017 Intel Corporation * Copyright (c) 2018 Intel Corporation
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -172,3 +172,32 @@ void setup_ownership_i2s(void)
I2S_OWNSEL(2) | I2S_OWNSEL(3); I2S_OWNSEL(2) | I2S_OWNSEL(3);
*(volatile u32_t *)SUE_DSPIOPO_REG |= value; *(volatile u32_t *)SUE_DSPIOPO_REG |= value;
} }
u32_t soc_get_ref_clk_freq(void)
{
u32_t bootstrap;
static u32_t freq = 0;
if (0 == freq) {
/* if bootstraps have not been read before, read them */
bootstrap = *((volatile u32_t *)SOC_S1000_GLB_CTRL_STRAPS);
bootstrap &= SOC_S1000_STRAP_REF_CLK;
switch (bootstrap) {
case SOC_S1000_STRAP_REF_CLK_19P2:
freq = 19200000;
break;
case SOC_S1000_STRAP_REF_CLK_24P576:
freq = 24576000;
break;
case SOC_S1000_STRAP_REF_CLK_38P4:
default:
freq = 38400000;
break;
}
}
return freq;
}

14
arch/xtensa/soc/intel_s1000/soc.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017 Intel Corporation * Copyright (c) 2018 Intel Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -107,6 +107,8 @@
#define SSP_SIZE 0x0000200 #define SSP_SIZE 0x0000200
#define SSP_BASE(x) (0x00077000 + (x) * SSP_SIZE) #define SSP_BASE(x) (0x00077000 + (x) * SSP_SIZE)
#define SSP_MN_DIV_BASE (0x00078D00)
#define SOC_INTEL_S1000_MCK_XTAL_FREQ_HZ 38400000 #define SOC_INTEL_S1000_MCK_XTAL_FREQ_HZ 38400000
@ -119,6 +121,15 @@
#define USB_DW_BASE 0x000A0000 #define USB_DW_BASE 0x000A0000
#define USB_DW_IRQ 0x00000806 #define USB_DW_IRQ 0x00000806
/* Global Control registers */
#define SOC_S1000_GLB_CTRL_BASE (0x00081C00)
#define SOC_S1000_GLB_CTRL_STRAPS (SOC_S1000_GLB_CTRL_BASE + 0x40)
#define SOC_S1000_STRAP_REF_CLK (BIT_MASK(2) << 3)
#define SOC_S1000_STRAP_REF_CLK_38P4 (0 << 3)
#define SOC_S1000_STRAP_REF_CLK_19P2 (1 << 3)
#define SOC_S1000_STRAP_REF_CLK_24P576 (2 << 3)
extern void _soc_irq_enable(u32_t irq); extern void _soc_irq_enable(u32_t irq);
extern void _soc_irq_disable(u32_t irq); extern void _soc_irq_disable(u32_t irq);
extern void setup_ownership_dma0(void); extern void setup_ownership_dma0(void);
@ -126,5 +137,6 @@ extern void setup_ownership_dma1(void);
extern void setup_ownership_dma2(void); extern void setup_ownership_dma2(void);
extern void dcache_writeback_region(void *addr, size_t size); extern void dcache_writeback_region(void *addr, size_t size);
extern void setup_ownership_i2s(void); extern void setup_ownership_i2s(void);
extern u32_t soc_get_ref_clk_freq(void);
#endif /* __INC_SOC_H */ #endif /* __INC_SOC_H */