soc: esp32s3: AMP support
Updates and fixes to support APPCPU. - fix ld scripts - fix and update memory layout - fix build issues - fix sysbuild Signed-off-by: Marek Matej <marek.matej@espressif.com>
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12 changed files with 557 additions and 291 deletions
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@ -10,24 +10,16 @@
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#include "memory.h"
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/* The "user_iram_end" represents the 2nd stage bootloader
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* "iram_loader_seg" start address (that should not be overlapped).
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* If no bootloader is used, we can extend it to gain more user ram.
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*/
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#ifdef CONFIG_ESP_SIMPLE_BOOT
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user_iram_end = (BOOTLOADER_USER_DRAM_END + IRAM_DRAM_OFFSET);
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#else
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user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START;
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#endif
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/* User available SRAM memory segments */
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user_dram_seg_org = SRAM1_DRAM_START;
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user_iram_seg_org = SRAM0_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE;
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user_dram_end = BOOTLOADER_IRAM_LOADER_SEG_START - IRAM_DRAM_OFFSET;
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user_idram_size = user_dram_end - SRAM1_DRAM_START;
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sram0_iram_size = SRAM0_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE;
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user_iram_seg_len = user_idram_size + sram0_iram_size;
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user_dram_seg_len = user_idram_size;
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amp_total_size = APPCPU_SRAM_TOTAL_SIZE;
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procpu_iram_end = USER_IRAM_END - APPCPU_SRAM_TOTAL_SIZE;
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procpu_dram_end = USER_DRAM_END - APPCPU_SRAM_TOTAL_SIZE;
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procpu_iram_org = SRAM_USER_IRAM_START;
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procpu_iram_len = procpu_iram_end - procpu_iram_org;
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procpu_dram_org = SRAM1_DRAM_START;
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procpu_dram_len = procpu_dram_end - procpu_dram_org;
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/* Aliases */
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#define FLASH_CODE_REGION irom0_0_seg
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@ -36,6 +28,7 @@ user_dram_seg_len = user_idram_size;
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#define RAMABLE_REGION dram0_0_seg
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#define ROMABLE_REGION FLASH
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/* Zephyr macro re-definitions */
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#undef GROUP_DATA_LINK_IN
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#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion
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@ -66,14 +59,13 @@ MEMORY
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FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
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#endif /* CONFIG_BOOTLOADER_MCUBOOT */
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iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len - APPCPU_IRAM_SIZE
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dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len - APPCPU_DRAM_SIZE
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iram0_0_seg(RX): org = procpu_iram_org, len = procpu_iram_len
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dram0_0_seg(RW): org = procpu_dram_org, len = procpu_dram_len
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irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
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drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
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/**
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* `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region.
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/* The `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region.
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* A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
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*/
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#if defined(CONFIG_ESP_SPIRAM)
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@ -101,11 +93,15 @@ MEMORY
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ENTRY(CONFIG_KERNEL_ENTRY)
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/* Used as a pointer to the heap end */
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#ifdef CONFIG_SOC_ENABLE_APPCPU
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_heap_sentry = procpu_dram_end;
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#else
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_heap_sentry = DRAM_RESERVED_START;
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#endif
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SECTIONS
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{
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_iram_dram_offset = IRAM_DRAM_OFFSET;
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_iram_dram_offset = IRAM_DRAM_OFFSET;
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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/* Reserve space for MCUboot header in the binary */
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@ -116,6 +112,7 @@ SECTIONS
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QUAD(0x0)
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QUAD(0x0)
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} > mcuboot_hdr
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/* Image load table */
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.metadata :
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{
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/* 0. Magic byte for load header */
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@ -144,7 +141,6 @@ SECTIONS
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} > metadata
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#endif /* CONFIG_BOOTLOADER_MCUBOOT */
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/* Virtual non-loadable sections */
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#include <zephyr/linker/rel-sections.ld>
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@ -275,7 +271,9 @@ SECTIONS
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*(.entry.text)
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*(.init.literal)
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*(.init)
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_init_end = ABSOLUTE(.);
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} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
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.iram0.text : ALIGN(4)
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@ -310,6 +308,11 @@ SECTIONS
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*libphy.a:(.phyiram .phyiram.*)
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*libgcov.a:(.literal .text .literal.* .text.*)
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/* APPCPU_ENABLED */
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*libzephyr.a:esp32s3-mp.*(.literal .text .literal.* .text.*)
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*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
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*libzephyr.a:flash_mmap.*(.literal .text .literal.* .text.*)
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/* [mapping:esp_psram] */
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*libzephyr.a:mmu_psram_flash.*(.literal .literal.* .text .text.*)
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*libzephyr.a:esp_psram_impl_quad.*(.literal .literal.* .text .text.*)
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@ -550,6 +553,11 @@ SECTIONS
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*libzephyr.a:esp_mmu_map.*(.rodata .rodata.*)
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*libdrivers__interrupt_controller.a:(.rodata .rodata.*)
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/* APPCPU_ENABLE */
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*libzephyr.a:esp32s3-mp.*(.rodata .rodata.*)
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*libzephyr.a:bootloader_flash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
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*libzephyr.a:flash_mmap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
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/* [mapping:esp_psram] */
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*libzephyr.a:mmu_psram_flash.*(.rodata .rodata.*)
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*libzephyr.a:esp_psram_impl_octal.*(.rodata .rodata.*)
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@ -798,6 +806,10 @@ SECTIONS
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} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
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/* --- END OF IROM --- */
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/* --- START OF DROM --- */
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/* This dummy section represents the .flash.text section but in default_rodata_seg.
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* Thus, it must have its alignment and (at least) its size.
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*/
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@ -879,6 +891,10 @@ SECTIONS
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_image_rodata_end = ABSOLUTE(.);
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} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
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/* --- END OF DROM --- */
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/* --- START OF SPIRAM --- */
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/**
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* This section is required to skip flash rodata sections, because `ext_ram_seg`
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* and `drom0_0_seg` are on the same bus
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@ -907,8 +923,9 @@ SECTIONS
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#endif /* CONFIG_ESP_SPIRAM */
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/* --- XTENSA GLUE AND DEBUG BEGIN --- */
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/* --- END OF SPIRAM --- */
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/* --- XTENSA GLUE AND DEBUG BEGIN --- */
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <zephyr/linker/intlist.ld>
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#endif
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