soc: renesas: Add initial support for RA6E1 SoC

Initial commit to support RA6E1 SoC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: default avatarQuy Tran <quy.tran.pz@renesas.com>

dts/arm/renesas/ra/ra6/r7fa6e10f2cfp.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/r7fa6e10x.dtsi>
+
+/ {
+	soc {
+		flash-controller@407e0000 {
+			reg = <0x407e0000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0x0 DT_SIZE_M(1)>;
+			};
+		};
+	};
+};

dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi

@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(256)>;
+		};
+
+		ioport6: gpio@400800c0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x400800c0 0x20>;
+			port = <6>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport7: gpio@400800e0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x400800e0 0x20>;
+			port = <7>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		sci1: sci1@40118100 {
+			compatible = "renesas,ra-sci";
+			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40118100 0x100>;
+			clocks = <&pclka MSTPB 30>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <1>;
+				status = "disabled";
+			};
+		};
+
+		sci2: sci2@40118200 {
+			compatible = "renesas,ra-sci";
+			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40118200 0x100>;
+			clocks = <&pclka MSTPB 29>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <2>;
+				status = "disabled";
+			};
+		};
+
+		sci3: sci3@40118300 {
+			compatible = "renesas,ra-sci";
+			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40118300 0x100>;
+			clocks = <&pclka MSTPB 28>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <3>;
+				status = "disabled";
+			};
+		};
+
+		sci4: sci4@40118400 {
+			compatible = "renesas,ra-sci";
+			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40118400 0x100>;
+			clocks = <&pclka MSTPB 27>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <4>;
+				status = "disabled";
+			};
+		};
+	};
+
+	clocks: clocks {
+		xtal: clock-xtal {
+			compatible = "renesas,ra-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(20)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(20)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL */
+			source = <RA_PLL_SOURCE_HOCO>;
+			div = <RA_PLL_DIV_2>;
+			mul = <20 0>;
+			status = "disabled";
+		};
+
+		pll2: pll2 {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL2 */
+			source = <RA_PLL_SOURCE_DISABLE>;
+			div = <RA_PLL_DIV_2>;
+			mul = <20 0>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock {
+			compatible = "renesas,ra-cgc-pclk-block";
+			#clock-cells = <0>;
+			sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+		};
+	};
+};

soc/renesas/ra/ra6e1/CMakeLists.txt

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra6e1/Kconfig

@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6E1
+	select ARM
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select HAS_RENESAS_RA_FSP
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select FPU
+	select HAS_SWO
+	select XIP

soc/renesas/ra/ra6e1/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA6E1
+
+config NUM_IRQS
+	default 96
+
+config PINCTRL
+	default y
+
+endif # SOC_SERIES_RA6E1

soc/renesas/ra/ra6e1/Kconfig.soc

@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA6E1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+	  Renesas RA6E1 series
+
+config SOC_R7FA6E10F2CFP
+	bool
+	select SOC_SERIES_RA6E1
+	help
+	  R7FA6E10F2CFP
+
+config SOC_SERIES
+	default "ra6e1" if SOC_SERIES_RA6E1
+
+config SOC
+	default "r7fa6e10f2cfp" if SOC_R7FA6E10F2CFP

soc/renesas/ra/ra6e1/sections.ld

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+	. = ALIGN(4);
+	__Code_In_RAM_Start = .;
+	KEEP(*(.code_in_ram*))
+	__Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+	__OPTION_SETTING_OFS_Start = .;
+	KEEP(*(.option_setting_ofs0))
+	. = __OPTION_SETTING_OFS_Start + 0x04;
+	KEEP(*(.option_setting_ofs2))
+	. = __OPTION_SETTING_OFS_Start + 0x10;
+	KEEP(*(.option_setting_dualsel))
+	__OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+	__OPTION_SETTING_SAS_Start = .;
+	KEEP(*(.option_setting_sas))
+	__OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+	__OPTION_SETTING_S_Start = .;
+	KEEP(*(.option_setting_ofs1_sec))
+	. = __OPTION_SETTING_S_Start + 0x04;
+	KEEP(*(.option_setting_ofs3_sec))
+	. = __OPTION_SETTING_S_Start + 0x10;
+	KEEP(*(.option_setting_banksel_sec))
+	. = __OPTION_SETTING_S_Start + 0x40;
+	KEEP(*(.option_setting_bps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x44;
+	KEEP(*(.option_setting_bps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x48;
+	KEEP(*(.option_setting_bps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x4C;
+	KEEP(*(.option_setting_bps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x60;
+	KEEP(*(.option_setting_pbps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x64;
+	KEEP(*(.option_setting_pbps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x68;
+	KEEP(*(.option_setting_pbps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x6C;
+	KEEP(*(.option_setting_pbps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x80;
+	KEEP(*(.option_setting_ofs1_sel))
+	. = __OPTION_SETTING_S_Start + 0x84;
+	KEEP(*(.option_setting_ofs3_sel))
+	. = __OPTION_SETTING_S_Start + 0x90;
+	KEEP(*(.option_setting_banksel_sel))
+	. = __OPTION_SETTING_S_Start + 0xC0;
+	KEEP(*(.option_setting_bps_sel0))
+	. = __OPTION_SETTING_S_Start + 0xC4;
+	KEEP(*(.option_setting_bps_sel1))
+	. = __OPTION_SETTING_S_Start + 0xC8;
+	KEEP(*(.option_setting_bps_sel2))
+	. = __OPTION_SETTING_S_Start + 0xCC;
+	KEEP(*(.option_setting_bps_sel3))
+	__OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF

soc/renesas/ra/ra6e1/soc.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA6E1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra6e1_init(void)
+{
+	uint32_t key;
+
+	extern volatile uint16_t g_protect_counters[];
+	for (uint32_t i = 0; i < 4; i++) {
+		g_protect_counters[i] = 0;
+	}
+
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+	/* Disable protection using PRCR register. */
+	R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+	/* Initialize peripherals to secure mode for flat projects */
+	R_PSCU->PSARB = 0;
+	R_PSCU->PSARC = 0;
+	R_PSCU->PSARD = 0;
+	R_PSCU->PSARE = 0;
+
+	R_CPSCU->ICUSARG = 0;
+	R_CPSCU->ICUSARH = 0;
+	R_CPSCU->ICUSARI = 0;
+
+	/* Enable protection using PRCR register. */
+	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+
+	key = irq_lock();
+
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+	bsp_clock_init();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(renesas_ra6e1_init, PRE_KERNEL_1, 0);

soc/renesas/ra/ra6e1/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA6E1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_ */

soc/renesas/ra/soc.yml

@@ -19,3 +19,6 @@ family:
       - name: ra6m3
         socs:
           - name: r7fa6m3ah3cfc
+      - name: ra6e1
+        socs:
+          - name: r7fa6e10f2cfp