From ecd23f4fa3cbeb51b4cf594ed8b91ce3d53eafa3 Mon Sep 17 00:00:00 2001
From: Erwan Gouriou <erwan.gouriou@linaro.org>
Date: Wed, 19 Jun 2019 09:36:13 +0200
Subject: [PATCH] dts: STM32H747 basic device tree description

Initiate stm32h7 device tree description, with stm32h747 single core
configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
---
 dts/arm/st/h7/stm32h7.dtsi                    | 57 +++++++++++++++++++
 dts/arm/st/h7/stm32h747.dtsi                  |  7 +++
 dts/arm/st/h7/stm32h747Xi_m7.dtsi             | 29 ++++++++++
 .../st,stm32h7-flash-controller.yaml          | 15 +++++
 4 files changed, 108 insertions(+)
 create mode 100644 dts/arm/st/h7/stm32h7.dtsi
 create mode 100644 dts/arm/st/h7/stm32h747.dtsi
 create mode 100644 dts/arm/st/h7/stm32h747Xi_m7.dtsi
 create mode 100644 dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml

diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi
new file mode 100644
index 00000000000..e1a4315ef43
--- /dev/null
+++ b/dts/arm/st/h7/stm32h7.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m7";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		flash-controller@52002000 {
+			compatible = "st,stm32h7-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x52002000 0x400>;
+			interrupts = <4 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		rcc: rcc@58024400 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x58024400 0x400>;
+			label = "STM32_CLK_RCC";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/h7/stm32h747.dtsi b/dts/arm/st/h7/stm32h747.dtsi
new file mode 100644
index 00000000000..4343a0cfc2c
--- /dev/null
+++ b/dts/arm/st/h7/stm32h747.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7.dtsi>
diff --git a/dts/arm/st/h7/stm32h747Xi_m7.dtsi b/dts/arm/st/h7/stm32h747Xi_m7.dtsi
new file mode 100644
index 00000000000..a34a1aa39b0
--- /dev/null
+++ b/dts/arm/st/h7/stm32h747Xi_m7.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h747.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	/* system data RAM accessible over over AXI bus */
+	sram0: memory@24000000 {
+		device_type = "memory";
+		reg = <0x24000000 DT_SIZE_K(512)>;
+		compatible = "mmio-sram";
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml
new file mode 100644
index 00000000000..5d6eeebcb15
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml
@@ -0,0 +1,15 @@
+---
+title: STM32 H7 Flash Controller
+version: 0.1
+
+description: >
+    This binding gives a base representation of the STM32 H7 Flash Controller
+
+inherits:
+    !include flash-controller.yaml
+
+properties:
+    compatible:
+      constraint: "st,stm32h7-flash-controller"
+
+...