From ec6a98e5e1d204691e0a0049290da847a6b448ab Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Sat, 30 May 2020 07:27:52 -0700 Subject: [PATCH] drivers/timer/cavs_timer: Prevent spurious interrupts The HDA wall clock timer is a 64 bit timer with 64 bit compare registers, but it's being used from a 32 bit CPU. Writing the comparator piecewise with a 64 bit C assignment will write the low dword first, opening the possibility that the hardware will see time go "backwards" and trigger an interrupt incorrectly. Disable the enable bit while setting the comparator. Found by inspection. In practice this will be very rare, and spurious timer interrupts are supposed to be benign anyway (though they can result in timeout expirations being misaligned to ticks, which might be surprising to applications). Best to get it right. Signed-off-by: Andy Ross --- drivers/timer/cavs_timer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/timer/cavs_timer.c b/drivers/timer/cavs_timer.c index 2dbb655ffaf..b3ff58ff33b 100644 --- a/drivers/timer/cavs_timer.c +++ b/drivers/timer/cavs_timer.c @@ -36,6 +36,9 @@ static volatile struct soc_dsp_shim_regs *shim_regs = static void set_compare(uint64_t time) { + /* Disarm the comparator to prevent spurious triggers */ + shim_regs->dspwctcs &= ~DSP_WCT_CS_TA(TIMER); + #if (TIMER == 0) /* Set compare register */ shim_regs->dspwct0c = time;