drivers: can: sam: use UPLL clock instead of PLLA clock
Use the UPLLCK clock for the CAN controller as recommended by the Atmel SAM E70 data sheet. Move the configuration of the clock prescaler from Kconfig to devicetree and limit it to the values recommended by the SAM E70 datasheet. Fixes: #45012 Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
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03bece0b70
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4 changed files with 20 additions and 17 deletions
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@ -8,15 +8,3 @@ config CAN_SAM
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bool "Atmel SAM CAN driver"
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default $(dt_compat_enabled,$(DT_COMPAT_ATMEL_SAM_CAN))
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select CAN_MCAN
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if CAN_SAM
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config CAN_SAM_CKDIV
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int "Clock divider"
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range 0 255
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default 0
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depends on CAN_SAM
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help
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Clock divider for the MCAN core clock.
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endif #CAN_SAM
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@ -21,6 +21,7 @@ struct can_sam_config {
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void (*config_irq)(void);
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const struct pinctrl_dev_config *pcfg;
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uint8_t pmc_id;
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int divider;
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};
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struct can_sam_data {
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@ -29,18 +30,20 @@ struct can_sam_data {
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static int can_sam_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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ARG_UNUSED(dev);
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_sam_config *sam_cfg = mcan_cfg->custom;
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*rate = SOC_ATMEL_SAM_MCK_FREQ_HZ / (CONFIG_CAN_SAM_CKDIV + 1);
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*rate = SOC_ATMEL_SAM_UPLLCK_FREQ_HZ / (sam_cfg->divider);
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return 0;
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}
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static void can_sam_clock_enable(const struct can_sam_config *cfg)
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static void can_sam_clock_enable(const struct can_sam_config *sam_cfg)
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{
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REG_PMC_PCK5 = PMC_PCK_CSS_PLLA_CLK | PMC_PCK_PRES(CONFIG_CAN_SAM_CKDIV);
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REG_PMC_PCK5 = PMC_PCK_CSS_UPLL_CLK | PMC_PCK_PRES(sam_cfg->divider - 1);
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PMC->PMC_SCER |= PMC_SCER_PCK5;
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soc_pmc_peripheral_enable(cfg->pmc_id);
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soc_pmc_peripheral_enable(sam_cfg->pmc_id);
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}
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static int can_sam_init(const struct device *dev)
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@ -129,6 +132,7 @@ static void config_can_##inst##_irq(void)
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#define CAN_SAM_CFG_INST(inst) \
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static const struct can_sam_config can_sam_cfg_##inst = { \
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.pmc_id = DT_INST_PROP(inst, peripheral_id), \
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.divider = DT_INST_PROP(inst, divider), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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.config_irq = config_can_##inst##_irq, \
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}; \
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