drivers: pinmux: stm32: STM32F2 added ETH support to pinmux and use it

This patch adds support for Ethernet in the STM32F2 family of
microcontrollers and enables it for the the Nucleo-F207ZG.

Signed-off-by: Daniel Egger <daniel@eggers-club.de>

boards/arm/nucleo_f207zg/Kconfig.defconfig

@@ -17,4 +17,14 @@ config UART_STM32_PORT_3
 
 endif # UART_CONSOLE
 
+if NETWORKING
+
+config NET_L2_ETHERNET
+	def_bool y
+
+config ETH_STM32_HAL
+	def_bool y
+
+endif # NETWORKING
+
 endif # BOARD_NUCLEO_F207ZG

boards/arm/nucleo_f207zg/doc/nucleo_f207zg.rst

@@ -11,6 +11,7 @@ with a wide range of connectivity support and configurations. Here are
 some highlights of the Nucleo F207ZG board:
 
 - STM32 microcontroller in LQFP144 package
+- Ethernet compliant with IEEE-802.3-2002
 - Two types of extension resources:
 
   - ST Zio connector including: support for Arduino* Uno V3 connectivity
@@ -59,7 +60,9 @@ Nucleo F207ZG provides the following hardware components:
 - SDIO
 - USB 2.0 OTG FS
 - DMA Controller
+- 10/100 Ethernet MAC with dedicated DMA
 - CRC calculation unit
+- True random number generator
 
 More information about STM32F207ZG can be found here:
 
@@ -83,6 +86,8 @@ The Zephyr nucleo_207zg board configuration supports the following hardware feat
 +-----------+------------+-------------------------------------+
 | GPIO      | on-chip    | gpio                                |
 +-----------+------------+-------------------------------------+
+| ETHERNET  | on-chip    | Ethernet                            |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on this Zephyr port.
 
@@ -124,6 +129,7 @@ For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 Default Zephyr Peripheral Mapping:
 ----------------------------------
 
+- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13
 - USER_PB : PC13
 - LD1 : PB0
 - LD2 : PB7

boards/arm/nucleo_f207zg/pinmux.c

@@ -18,6 +18,19 @@ static const struct pin_config pinconf[] = {
 	{STM32_PIN_PD8, STM32F2_PINMUX_FUNC_PD8_USART3_TX},
 	{STM32_PIN_PD9, STM32F2_PINMUX_FUNC_PD9_USART3_RX},
 #endif /* #ifdef CONFIG_UART_STM32_PORT_3 */
+#ifdef CONFIG_ETH_STM32_HAL
+	{STM32_PIN_PC1, STM32F2_PINMUX_FUNC_PC1_ETH},
+	{STM32_PIN_PC4, STM32F2_PINMUX_FUNC_PC4_ETH},
+	{STM32_PIN_PC5, STM32F2_PINMUX_FUNC_PC5_ETH},
+
+	{STM32_PIN_PA1, STM32F2_PINMUX_FUNC_PA1_ETH},
+	{STM32_PIN_PA2, STM32F2_PINMUX_FUNC_PA2_ETH},
+	{STM32_PIN_PA7, STM32F2_PINMUX_FUNC_PA7_ETH},
+
+	{STM32_PIN_PG11, STM32F2_PINMUX_FUNC_PG11_ETH},
+	{STM32_PIN_PG13, STM32F2_PINMUX_FUNC_PG13_ETH},
+	{STM32_PIN_PB13, STM32F2_PINMUX_FUNC_PB13_ETH},
+#endif /* CONFIG_ETH_STM32_HAL */
 };
 
 static int pinmux_stm32_init(struct device *port)

drivers/pinmux/stm32/pinmux_stm32f2.h

@@ -14,12 +14,25 @@
 /* Port A */
 #define STM32F2_PINMUX_FUNC_PA1_UART4_RX    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
+#define STM32F2_PINMUX_FUNC_PA1_ETH         \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 
 #define STM32F2_PINMUX_FUNC_PA2_USART2_TX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
+#define STM32F2_PINMUX_FUNC_PA2_ETH         \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 
 #define STM32F2_PINMUX_FUNC_PA3_USART2_RX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
+#define STM32F2_PINMUX_FUNC_PA3_ETH         \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+
+#define STM32F2_PINMUX_FUNC_PA7_ETH         \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 
 #define STM32F2_PINMUX_FUNC_PA9_USART1_TX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
@@ -39,8 +52,31 @@
 
 #define STM32F2_PINMUX_FUNC_PB11_USART3_RX  \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
+#define STM32F2_PINMUX_FUNC_PB11_ETH        \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+
+#define STM32F2_PINMUX_FUNC_PB12_ETH        \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+
+#define STM32F2_PINMUX_FUNC_PB13_ETH        \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 
 /* Port C */
+#define STM32F2_PINMUX_FUNC_PC1_ETH         \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+
+#define STM32F2_PINMUX_FUNC_PC4_ETH         \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+
+#define STM32F2_PINMUX_FUNC_PC5_ETH         \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+
 #define STM32F2_PINMUX_FUNC_PC6_USART6_TX   \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
 
@@ -79,6 +115,17 @@
 /* Port F */
 
 /* Port G */
+#define STM32F2_PINMUX_FUNC_PG11_ETH        \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+
+#define STM32F2_PINMUX_FUNC_PG13_ETH        \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+
+#define STM32F2_PINMUX_FUNC_PG14_ETH        \
+	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
+	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 
 /* Port H */