soc: esp32: Update IRQ config for shared allocator

Update IRQ handling related files to unify interrupt controller
between Xtensa and RISCV devices.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>

soc/espressif/common/loader.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -252,7 +252,7 @@ void __start(void)
 {
 #ifdef CONFIG_RISCV_GP
 
-	__asm__ __volatile__("la t0, _esp_vector_table\n"
+	__asm__ __volatile__("la t0, _vector_table\n"
 			     "csrw mtvec, t0\n");
 
 	/* Disable normal interrupts. */

soc/espressif/esp32/soc.c

@@ -26,8 +26,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 	esp_flash_config();
 
-	esp_intr_initialize();
-
 #if CONFIG_ESP_SPIRAM
 	esp_init_psram();
 
@@ -47,8 +45,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 void IRAM_ATTR __esp_platform_mcuboot_start(void)
 {
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_prep_c();
 

soc/espressif/esp32/soc_appcpu.c

@@ -87,8 +87,6 @@ void IRAM_ATTR __appcpu_start(void)
 
 	core_intr_matrix_clear();
 
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_prep_c();
 

soc/espressif/esp32c2/CMakeLists.txt

@@ -3,7 +3,6 @@
 zephyr_sources(
   vectors.S
   soc_irq.S
-  soc_irq.c
   soc.c
   ../common/loader.c
   )

soc/espressif/esp32c2/Kconfig.defconfig

@@ -1,12 +1,10 @@
-# ESP32C2 SoC configuration
+# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
-
-# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_ESP32C2
 
 config NUM_IRQS
-	default 43
+	default 32
 
 config FLASH_SIZE
 	default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)

soc/espressif/esp32c2/soc.c

@@ -10,7 +10,7 @@
 #include <esp_private/cache_utils.h>
 #include <esp_private/system_internal.h>
 #include <esp_timer.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/kernel_structs.h>
 #include <kernel_internal.h>
 
@@ -24,8 +24,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 	esp_flash_config();
 
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_cstart();
 
@@ -34,8 +32,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 void IRAM_ATTR __esp_platform_mcuboot_start(void)
 {
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_cstart();
 

soc/espressif/esp32c2/soc_irq.S

@@ -1,4 +1,4 @@
-/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2021-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,13 +8,8 @@
 
 /* Exports */
 GTEXT(__soc_handle_irq)
-GTEXT(soc_intr_get_next_source)
 
 SECTION_FUNC(exception.other, __soc_handle_irq)
-	addi sp, sp,-4
+
-	sw  ra, 0x00(sp)
+	/* int status clearing is done at ISR */
-	la t1, soc_intr_get_next_source
-	jalr ra, t1, 0
-	lw  ra, 0x00(sp)
-	addi sp, sp, 4
 	ret

soc/espressif/esp32c2/soc_irq.c

@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <soc/rtc_cntl_reg.h>
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <soc/gpio_reg.h>
-#include <soc/syscon_reg.h>
-#include <soc/system_reg.h>
-#include <riscv/interrupt.h>
-#include <soc/interrupt_reg.h>
-#include <soc/periph_defs.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-
-#include <zephyr/kernel_structs.h>
-#include <string.h>
-#include <zephyr/toolchain.h>
-#include <soc.h>
-#include <zephyr/arch/riscv/arch.h>
-
-#define ESP32C2_INTSTATUS_SLOT1_THRESHOLD	32
-
-void arch_irq_enable(unsigned int irq)
-{
-	esp_intr_enable(irq);
-}
-
-void arch_irq_disable(unsigned int irq)
-{
-	esp_intr_disable(irq);
-}
-
-int arch_irq_is_enabled(unsigned int irq)
-{
-	bool res = false;
-	uint32_t key = irq_lock();
-
-	if (irq < 32) {
-		res = esp_intr_get_enabled_intmask(0) & BIT(irq);
-	} else {
-		res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
-	}
-
-	irq_unlock(key);
-
-	return res;
-}
-
-uint32_t soc_intr_get_next_source(void)
-{
-	uint32_t status;
-	uint32_t source;
-
-	status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_0_REG) &
-		esp_intr_get_enabled_intmask(0);
-
-	if (status) {
-		source = __builtin_ffs(status) - 1;
-	} else {
-		status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_1_REG) &
-			esp_intr_get_enabled_intmask(1);
-		source = (__builtin_ffs(status) - 1 + ESP32C2_INTSTATUS_SLOT1_THRESHOLD);
-	}
-
-	return source;
-}

soc/espressif/esp32c2/vectors.S

@@ -1,4 +1,4 @@
-/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2020-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,12 +22,12 @@ GTEXT(_isr_wrapper)
 	 * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
 	 */
 
-	.global  _esp_vector_table
+	.global  _vector_table
 	.section .exception_vectors.text
 	.balign   0x100
-	.type     _esp_vector_table, @function
+	.type     _vector_table, @function
 
-_esp_vector_table:
+_vector_table:
 	.option push
 	.option norvc
 	.rept (32)

soc/espressif/esp32c3/CMakeLists.txt

@@ -3,7 +3,6 @@
 zephyr_sources(
   vectors.S
   soc_irq.S
-  soc_irq.c
   soc.c
   ../common/loader.c
   )

soc/espressif/esp32c3/Kconfig.defconfig

@@ -1,10 +1,10 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_ESP32C3
 
 config NUM_IRQS
-	default 62
+	default 32
 
 config FLASH_SIZE
 	default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)

soc/espressif/esp32c3/soc.c

@@ -11,7 +11,7 @@
 #include <esp_private/cache_utils.h>
 #include <esp_private/system_internal.h>
 #include <esp_timer.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/kernel_structs.h>
 #include <kernel_internal.h>
 
@@ -25,8 +25,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 	esp_flash_config();
 
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_cstart();
 
@@ -35,8 +33,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 void IRAM_ATTR __esp_platform_mcuboot_start(void)
 {
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_cstart();
 

soc/espressif/esp32c3/soc_irq.S

@@ -1,4 +1,4 @@
-/* Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2021-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,13 +8,8 @@
 
 /* Exports */
 GTEXT(__soc_handle_irq)
-GTEXT(soc_intr_get_next_source)
 
 SECTION_FUNC(exception.other, __soc_handle_irq)
-	addi sp, sp,-4
+
-	sw  ra, 0x00(sp)
+	/* int status clearing is done at ISR */
-	la t1, soc_intr_get_next_source
-	jalr ra, t1, 0
-	lw  ra, 0x00(sp)
-	addi sp, sp, 4
 	ret

soc/espressif/esp32c3/soc_irq.c

@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <soc/rtc_cntl_reg.h>
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <soc/gpio_reg.h>
-#include <soc/syscon_reg.h>
-#include <soc/system_reg.h>
-#include <riscv/interrupt.h>
-#include <soc/interrupt_reg.h>
-#include <soc/periph_defs.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-
-#include <zephyr/kernel_structs.h>
-#include <string.h>
-#include <zephyr/toolchain.h>
-#include <soc.h>
-#include <zephyr/arch/riscv/arch.h>
-
-#define ESP32C3_INTSTATUS_SLOT1_THRESHOLD	32
-
-void arch_irq_enable(unsigned int irq)
-{
-	esp_intr_enable(irq);
-}
-
-void arch_irq_disable(unsigned int irq)
-{
-	esp_intr_disable(irq);
-}
-
-int arch_irq_is_enabled(unsigned int irq)
-{
-	bool res = false;
-	uint32_t key = irq_lock();
-
-	if (irq < 32) {
-		res = esp_intr_get_enabled_intmask(0) & BIT(irq);
-	} else {
-		res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
-	}
-
-	irq_unlock(key);
-
-	return res;
-}
-
-uint32_t soc_intr_get_next_source(void)
-{
-	uint32_t status;
-	uint32_t source;
-
-	status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_0_REG) &
-		esp_intr_get_enabled_intmask(0);
-
-	if (status) {
-		source = __builtin_ffs(status) - 1;
-	} else {
-		status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_1_REG) &
-			esp_intr_get_enabled_intmask(1);
-		source = (__builtin_ffs(status) - 1 + ESP32C3_INTSTATUS_SLOT1_THRESHOLD);
-	}
-
-	return source;
-}

soc/espressif/esp32c3/vectors.S

@@ -1,4 +1,4 @@
-/* Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2020-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,12 +22,12 @@ GTEXT(_isr_wrapper)
 	 * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
 	 */
 
-  .global  _esp_vector_table
+	.global  _vector_table
 	.section .exception_vectors.text
 	.balign   0x100
-	.type     _esp_vector_table, @function
+	.type     _vector_table, @function
 
-_esp_vector_table:
+_vector_table:
 	.option push
 	.option norvc
 	.rept (32)

soc/espressif/esp32c6/CMakeLists.txt

@@ -3,7 +3,6 @@
 zephyr_sources_ifdef(CONFIG_SOC_ESP32C6_HPCORE
   vectors.S
   soc_irq.S
-  soc_irq.c
   soc.c
   ../common/loader.c
   )

soc/espressif/esp32c6/Kconfig.defconfig

@@ -1,12 +1,10 @@
-# ESP32C6 board configuration
+# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
-
-# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_ESP32C6
 
 config NUM_IRQS
-	default 77
+	default 32
 
 config FLASH_SIZE
 	default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)

soc/espressif/esp32c6/soc.c

@@ -10,7 +10,7 @@
 #include <esp_private/cache_utils.h>
 #include <esp_private/system_internal.h>
 #include <esp_timer.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/kernel_structs.h>
 #include <kernel_internal.h>
 
@@ -24,8 +24,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 	esp_flash_config();
 
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_cstart();
 
@@ -34,8 +32,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 void IRAM_ATTR __esp_platform_mcuboot_start(void)
 {
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_cstart();
 

soc/espressif/esp32c6/soc_irq.S

@@ -1,26 +1,15 @@
-/* Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2021-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <offsets.h>
+#include <zephyr/offsets.h>
 #include <zephyr/toolchain.h>
 
 /* Exports */
-GTEXT(__soc_is_irq)
 GTEXT(__soc_handle_irq)
-GTEXT(soc_intr_get_next_source)
-
-SECTION_FUNC(exception.other, __soc_is_irq)
-	csrr a0, mcause
-	srli a0, a0, 31
-	ret
 
 SECTION_FUNC(exception.other, __soc_handle_irq)
-	addi sp, sp,-4
+
-	sw  ra, 0x00(sp)
+	/* int status clearing is done at ISR */
-	la t1, soc_intr_get_next_source
-	jalr ra, t1, 0
-	lw  ra, 0x00(sp)
-	addi sp, sp, 4
 	ret

soc/espressif/esp32c6/soc_irq.c

@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <soc/gpio_reg.h>
-#include <soc/system_reg.h>
-#include <riscv/interrupt.h>
-#include <soc/interrupt_reg.h>
-#include <soc/periph_defs.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-
-#include <zephyr/kernel_structs.h>
-#include <string.h>
-#include <zephyr/toolchain/gcc.h>
-#include <soc.h>
-#include <zephyr/arch/riscv/arch.h>
-
-#define ESP32C6_INTSTATUS_REG1_THRESHOLD	32
-#define ESP32C6_INTSTATUS_REG2_THRESHOLD	64
-
-void arch_irq_enable(unsigned int irq)
-{
-	esp_intr_enable(irq);
-}
-
-void arch_irq_disable(unsigned int irq)
-{
-	esp_intr_disable(irq);
-}
-
-int arch_irq_is_enabled(unsigned int irq)
-{
-	bool res = false;
-	uint32_t key = irq_lock();
-
-	if (irq < 32) {
-		res = esp_intr_get_enabled_intmask(0) & BIT(irq);
-	} else if (irq < 64) {
-		res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
-	} else {
-		res = esp_intr_get_enabled_intmask(2) & BIT(irq - 64);
-	}
-
-	irq_unlock(key);
-
-	return res;
-}
-
-uint32_t soc_intr_get_next_source(void)
-{
-	uint32_t status;
-	uint32_t source = IRQ_NA;
-
-	/* Status register for interrupt sources 0 ~ 31 */
-	status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_0_REG) &
-		esp_intr_get_enabled_intmask(0);
-
-	if (status) {
-		source = __builtin_ffs(status) - 1;
-		goto ret;
-	}
-
-	/* Status register for interrupt sources 32 ~ 63 */
-	status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_1_REG) &
-		esp_intr_get_enabled_intmask(1);
-
-	if (status) {
-		source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG1_THRESHOLD);
-		goto ret;
-	}
-
-	/* Status register for interrupt sources 64 ~ 76 */
-	status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_2_REG) &
-		esp_intr_get_enabled_intmask(2);
-
-	if (status) {
-		source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG2_THRESHOLD);
-	}
-
-ret:
-	return source;
-}

soc/espressif/esp32c6/vectors.S

@@ -1,4 +1,4 @@
-/* Copyright 2023 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2020-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,12 +22,12 @@ GTEXT(_isr_wrapper)
 	 * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
 	 */
 
-	.global  _esp_vector_table
+	.global  _vector_table
 	.section .exception_vectors.text
 	.balign   0x100
-	.type     _esp_vector_table, @function
+	.type     _vector_table, @function
 
-_esp_vector_table:
+_vector_table:
 	.option push
 	.option norvc
 	.rept (32)

soc/espressif/esp32s2/soc.c

@@ -41,8 +41,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 	esp_flash_config();
 
-	esp_intr_initialize();
-
 #if CONFIG_ESP_SPIRAM
 	esp_init_psram();
 
@@ -62,8 +60,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 void IRAM_ATTR __esp_platform_mcuboot_start(void)
 {
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_prep_c();
 

soc/espressif/esp32s3/soc.c

@@ -54,8 +54,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 	esp_flash_config();
 
-	esp_intr_initialize();
-
 #if CONFIG_ESP_SPIRAM
 	esp_init_psram();
 
@@ -74,8 +72,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
 
 void IRAM_ATTR __esp_platform_mcuboot_start(void)
 {
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_prep_c();
 

soc/espressif/esp32s3/soc_appcpu.c

@@ -72,8 +72,6 @@ void IRAM_ATTR __appcpu_start(void)
 
 	core_intr_matrix_clear();
 
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_prep_c();