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soc: esp32: Update IRQ config for shared allocator

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Update IRQ handling related files to unify interrupt controller
between Xtensa and RISCV devices.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Raffael Rostagno 2025-02-21 15:34:31 -03:00 • committed by Benjamin Cabé
commit eb606a8e7d
24 changed files with 35 additions and 315 deletions
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4
soc/espressif/esp32s3/soc.c
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@ -54,8 +54,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
esp_flash_config();
esp_intr_initialize();
#if CONFIG_ESP_SPIRAM
esp_init_psram();
@ -74,8 +72,6 @@ void IRAM_ATTR __esp_platform_app_start(void)
void IRAM_ATTR __esp_platform_mcuboot_start(void)
{
esp_intr_initialize();
/* Start Zephyr */
z_prep_c();