diff --git a/drivers/gpio/gpio_stm32.h b/drivers/gpio/gpio_stm32.h index 0abededc786..e4650101d7c 100644 --- a/drivers/gpio/gpio_stm32.h +++ b/drivers/gpio/gpio_stm32.h @@ -102,6 +102,14 @@ #define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG #define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH #define STM32_PERIPH_GPIOI LL_AHB2_GRP1_PERIPH_GPIOI +#elif CONFIG_SOC_SERIES_STM32WBX +#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2 +#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA +#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB +#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC +#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD +#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE +#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH #endif /* CONFIG_SOC_SERIES_.. */ #ifdef CONFIG_SOC_SERIES_STM32F1X diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi index 36d293619ff..2723aad57b0 100644 --- a/dts/arm/st/wb/stm32wb.dtsi +++ b/dts/arm/st/wb/stm32wb.dtsi @@ -5,6 +5,8 @@ */ #include +#include +#include / { cpus { @@ -46,6 +48,67 @@ reg = <0x58000000 0x400>; label = "STM32_CLK_RCC"; }; + + pinctrl: pin-controller@48000000 { + compatible = "st,stm32-pinmux"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x48000000 0x2000>; + + gpioa: gpio@48000000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>; + label = "GPIOA"; + }; + + gpiob: gpio@48000400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>; + label = "GPIOB"; + }; + + gpioc: gpio@48000800 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>; + label = "GPIOC"; + }; + + gpiod: gpio@48000c00 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000c00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; + label = "GPIOD"; + }; + + gpioe: gpio@48001000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; + label = "GPIOE"; + }; + + gpioh: gpio@48001c00 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001c00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>; + label = "GPIOH"; + }; + }; }; }; diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series index fd82f5f98ae..1259687a13d 100644 --- a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series +++ b/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series @@ -12,4 +12,17 @@ source "soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb*" config SOC_SERIES default "stm32wb" +if GPIO_STM32 + +config GPIO_STM32_PORTD + default y + +config GPIO_STM32_PORTE + default y + +config GPIO_STM32_PORTH + default y + +endif # GPIO_STM32 + endif # SOC_SERIES_STM32WBX diff --git a/soc/arm/st_stm32/stm32wb/dts_fixup.h b/soc/arm/st_stm32/stm32wb/dts_fixup.h index c2888e5da5e..c07a4e3dff1 100644 --- a/soc/arm/st_stm32/stm32wb/dts_fixup.h +++ b/soc/arm/st_stm32/stm32wb/dts_fixup.h @@ -8,4 +8,58 @@ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_48000000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_48000000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_48000000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_48000000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_48000000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_48000400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_48000400_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_48000400_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_48000400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_48000400_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_48000800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_48000800_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_48000800_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_48000800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_48000800_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_48000C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_48000C00_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_48000C00_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_48000C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_48000C00_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_48001000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_48001000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_48001000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_48001000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_48001000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_48001C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_48001C00_LABEL +#define DT_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_48001C00_SIZE +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_48001C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_48001C00_CLOCK_BUS + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32wb/soc.h b/soc/arm/st_stm32/stm32wb/soc.h index 48fafa38b30..3d1a98e9b5e 100644 --- a/soc/arm/st_stm32/stm32wb/soc.h +++ b/soc/arm/st_stm32/stm32wb/soc.h @@ -27,6 +27,10 @@ */ #include +#ifdef CONFIG_GPIO_STM32 +#include +#endif + #ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE #include #include