boards: frdm_mcxn947: Add support for frdm_mcxn947 board

Add support for frdm_mcxn947 board

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>`
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>

boards/nxp/frdm_mcxn947/CMakeLists.txt

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+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)

boards/nxp/frdm_mcxn947/Kconfig

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+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INIT_PRIORITY
+	int "Board initialization priority"
+	default 1
+	help
+	  Board initialization priority.

boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947

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+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXN947
+	select SOC_MCXN947_CPU0 if BOARD_FRDM_MCXN947_MCXN947_CPU0
+	select SOC_MCXN947_CPU1 if BOARD_FRDM_MCXN947_MCXN947_CPU1
+	select SOC_PART_NUMBER_MCXN947VDF

boards/nxp/frdm_mcxn947/board.c

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+/*
+ * Copyright 2024  NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+
+/* Board xtal frequency in Hz */
+#define BOARD_XTAL0_CLK_HZ                        24000000U
+/* Core clock frequency: 150MHz */
+#define CLOCK_INIT_CORE_CLOCK                     150000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+__ramfunc static void enable_lpcac(void)
+{
+	SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
+	SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK |
+				SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK);
+}
+
+/* Update Active mode voltage for OverDrive mode. */
+void power_mode_od(void)
+{
+	/* Set the DCDC VDD regulator to 1.2 V voltage level */
+	spc_active_mode_dcdc_option_t opt = {
+		.DCDCVoltage       = kSPC_DCDC_OverdriveVoltage,
+		.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
+	};
+	SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
+
+	/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
+	spc_active_mode_core_ldo_option_t ldo_opt = {
+		.CoreLDOVoltage       = kSPC_CoreLDO_OverDriveVoltage,
+		.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
+	};
+	SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);
+
+	/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
+	spc_sram_voltage_config_t cfg = {
+		.operateVoltage       = kSPC_sramOperateAt1P2V,
+		.requestVoltageUpdate = true,
+	};
+	SPC_SetSRAMOperateVoltage(SPC0, &cfg);
+}
+
+static int frdm_mcxn947_init(void)
+{
+	/* Do not re-run this clock init code if using MCUBoot */
+#ifndef CONFIG_BOOTLOADER_MCUBOOT
+	enable_lpcac();
+
+	power_mode_od();
+
+	/* Enable SCG clock */
+	CLOCK_EnableClock(kCLOCK_Scg);
+
+	/* FRO OSC setup - begin, enable the FRO for safety switching */
+
+	/* Switch to FRO 12M first to ensure we can change the clock setting */
+	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+	/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
+	FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
+
+	/* Enable FRO HF(48MHz) output */
+	CLOCK_SetupFROHFClocking(48000000U);
+
+	/* Set up PLL0 */
+	const pll_setup_t pll0Setup = {
+		.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
+			   SCG_APLLCTRL_SELP(13U),
+		.pllndiv = SCG_APLLNDIV_NDIV(8U),
+		.pllpdiv = SCG_APLLPDIV_PDIV(1U),
+		.pllmdiv = SCG_APLLMDIV_MDIV(50U),
+		.pllRate = 150000000U
+	};
+	/* Configure PLL0 to the desired values */
+	CLOCK_SetPLL0Freq(&pll0Setup);
+	/* PLL0 Monitor is disabled */
+	CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);
+
+	/* Switch MAIN_CLK to PLL0 */
+	CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
+
+	/* Set AHBCLKDIV divider to value 1 */
+	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);
+#endif /* CONFIG_BOOTLOADER_MCUBOOT */
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer), okay)
+	CLOCK_AttachClk(kCLK_1M_to_OSTIMER);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio1);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio2);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio3);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio4);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio5);
+#endif
+
+	/* Set SystemCoreClock variable. */
+	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+
+	return 0;
+}
+
+SYS_INIT(frdm_mcxn947_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);

boards/nxp/frdm_mcxn947/board.cmake

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+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_SOC_MCXN947_CPU0)
+  board_runner_args(jlink "--device=MCXN947_M33_0" "--reset-after-load")
+  board_runner_args(linkserver  "--device=MCXN947:MCX-N9XX-EVK:cm33_core0")
+  board_runner_args(linkserver  "--override=/device/memory/1/flash-driver=MCXN9xx_S.cfx")
+  board_runner_args(linkserver  "--override=/device/memory/1/location=0x10000000")
+else()
+  message(FATAL_ERROR "Support for cpu1 not available yet")
+endif()
+
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nxp/frdm_mcxn947/board.yml

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+board:
+  name: frdm_mcxn947
+  vendor: nxp
+  socs:
+  - name: mcxn947

boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi

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+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXN947VDF-pinctrl.h>
+
+&pinctrl {
+	pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart {
+		group0 {
+			pinmux = <FC4_P0_PIO1_8>,
+				<FC4_P1_PIO1_9>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+};

boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi

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+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "frdm_mcxn947-pinctrl.dtsi"
+
+/ {
+	aliases{
+		led0 = &red_led;
+		led1 = &green_led;
+		led2 = &blue_led;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led: led_1 {
+			gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
+			label = "Green LED";
+			status = "disabled";
+		};
+		blue_led: led_2 {
+			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+			label = "Blue LED";
+			status = "disabled";
+		};
+		red_led: led_3 {
+			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+			label = "Red LED";
+			status = "disabled";
+		};
+	};
+};
+
+&flexcomm4_lpuart4 {
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_flexcomm4_lpuart>;
+	pinctrl-names = "default";
+};
+
+/*
+ * MCXN947 board uses OS timer as the kernel timer
+ * In case we need to switch to SYSTICK timer, then
+ * replace &os_timer with &systick
+ */
+&os_timer {
+	status = "okay";
+};

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts

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+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxn94x.dtsi>
+#include "frdm_mcxn947.dtsi"
+
+/ {
+	model = "NXP FRDM_N94 board";
+	compatible = "nxp,mcxn947", "nxp,mcx";
+
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	aliases{
+		sw0 = &user_button_3;
+		sw1 = &user_button_2;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,console = &flexcomm4_lpuart4;
+		zephyr,shell-uart = &flexcomm4_lpuart4;
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_2: button_0 {
+			label = "User SW2";
+			gpios = <&gpio0 29 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+		};
+		user_button_3: button_1 {
+			label = "User SW3";
+			gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+		};
+	};
+};
+
+/*
+ * Default for this board is to allocate SRAM0-5 to cpu0 but the
+ * application can have an application specific device tree to
+ * allocate the SRAM0-7 differently.
+ *
+ * For example, SRAM0-6 could be allocated to cpu0 with only SRAM7
+ * for cpu1. This would require the value of sram0 to have a DT_SIZE_K
+ * of 384. You would have to make updates to cpu1 sram settings as well.
+ */
+&sram0 {
+	compatible = "mmio-sram";
+	reg = <0x20000000 DT_SIZE_K(320)>;
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&green_led {
+	status = "okay";
+};
+
+&red_led {
+	status = "okay";
+};
+
+&flexcomm4 {
+	status = "okay";
+};
+
+&flexcomm4_lpuart4 {
+	status = "okay";
+};

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml

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+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: frdm_mcxn947/mcxn947/cpu0
+name: NXP FRDM MCXN947 (CPU0)
+type: mcu
+arch: arm
+ram: 320
+flash: 2048
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - arduino_serial
+  - gpio
+vendor: nxp

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig

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+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+CONFIG_PINCTRL=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_TRUSTED_EXECUTION_SECURE=y