diff --git a/drivers/adc/adc_npcx.c b/drivers/adc/adc_npcx.c index 119a61f72aa..6a5a1ad802a 100644 --- a/drivers/adc/adc_npcx.c +++ b/drivers/adc/adc_npcx.c @@ -41,12 +41,6 @@ LOG_MODULE_REGISTER(adc_npcx, CONFIG_ADC_LOG_LEVEL); #define ADC_NPCX_THRVAL_RESOLUTION 10 #define ADC_NPCX_THRVAL_MAX BIT_MASK(ADC_NPCX_THRVAL_RESOLUTION) -/* ADC threshold detection registers */ -#define THRCTL(dev, ctl_no) (*((volatile uint16_t *) npcx_thrctl_reg(dev, ctl_no))) -#ifdef CONFIG_SOC_SERIES_NPCX4 -#define THEN(dev) (*((volatile uint16_t *) npcx_then_reg(dev))) -#endif - /* Device config */ struct adc_npcx_config { /* adc controller base address */ @@ -57,8 +51,6 @@ struct adc_npcx_config { const uint8_t channel_count; /* amount of thresholds supported */ const uint8_t threshold_count; - /* threshold control register offset */ - const uint16_t threshold_reg_offset; /* routine for configuring ADC's ISR */ void (*irq_cfg_func)(void); const struct pinctrl_dev_config *pcfg; @@ -170,38 +162,23 @@ static inline void adc_npcx_config_channels(const struct device *dev, uint32_t c } } -static inline uint32_t npcx_thrctl_reg(const struct device *dev, - uint32_t ctl_no) -{ - const struct adc_npcx_config *config = dev->config; - - return (config->base + config->threshold_reg_offset) + (ctl_no - 1) * 2; -} - -#ifdef CONFIG_SOC_SERIES_NPCX4 -static inline uint32_t npcx_then_reg(const struct device *dev) -{ - const struct adc_npcx_config *config = dev->config; - - return (config->base + config->threshold_reg_offset + 0x10); -} -#endif - static inline void adc_npcx_enable_threshold_detect(const struct device *dev, uint8_t th_sel, bool enable) { + const struct adc_npcx_config *config = dev->config; + if (enable) { #ifdef CONFIG_SOC_SERIES_NPCX4 - THEN(dev) |= BIT(th_sel); + THEN(config->base) |= BIT(th_sel); #else - THRCTL(dev, (th_sel + 1)) |= BIT(NPCX_THRCTL_THEN); + THRCTL(config->base, th_sel) |= BIT(NPCX_THRCTL_THEN); #endif } else { #ifdef CONFIG_SOC_SERIES_NPCX4 - THEN(dev) &= ~BIT(th_sel); + THEN(config->base) &= ~BIT(th_sel); #else - THRCTL(dev, (th_sel + 1)) &= ~BIT(NPCX_THRCTL_THEN); + THRCTL(config->base, th_sel) &= ~BIT(NPCX_THRCTL_THEN); #endif } } @@ -616,16 +593,16 @@ static int adc_npcx_threshold_ctrl_setup(const struct device *dev, return -EINVAL; } - SET_FIELD(THRCTL(dev, (th_sel + 1)), + SET_FIELD(THRCTL(config->base, th_sel), NPCX_THRCTL_CHNSEL, t_ctrl->chnsel); if (t_ctrl->l_h) { - THRCTL(dev, (th_sel + 1)) |= BIT(NPCX_THRCTL_L_H); + THRCTL(config->base, th_sel) |= BIT(NPCX_THRCTL_L_H); } else { - THRCTL(dev, (th_sel + 1)) &= ~BIT(NPCX_THRCTL_L_H); + THRCTL(config->base, th_sel) &= ~BIT(NPCX_THRCTL_L_H); } /* Set the threshold value. */ - SET_FIELD(THRCTL(dev, (th_sel + 1)), NPCX_THRCTL_THRVAL, + SET_FIELD(THRCTL(config->base, th_sel), NPCX_THRCTL_THRVAL, t_ctrl->thrval); adc_context_release(&data->ctx, 0); @@ -879,7 +856,6 @@ static int adc_npcx_init(const struct device *dev) .clk_cfg = NPCX_DT_CLK_CFG_ITEM(n), \ .channel_count = DT_INST_PROP(n, channel_count), \ .threshold_count = DT_INST_PROP(n, threshold_count), \ - .threshold_reg_offset = DT_INST_PROP(n, threshold_reg_offset), \ .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ .irq_cfg_func = adc_npcx_irq_cfg_func_##n, \ }; \ diff --git a/dts/arm/nuvoton/npcx/npcx4.dtsi b/dts/arm/nuvoton/npcx/npcx4.dtsi index d1b5c7439e1..56adb416d01 100644 --- a/dts/arm/nuvoton/npcx/npcx4.dtsi +++ b/dts/arm/nuvoton/npcx/npcx4.dtsi @@ -259,7 +259,6 @@ /* ADC0 comparator configuration in npcx4 series */ adc0: adc@400d1000 { channel-count = <26>; - threshold-reg-offset = <0x80>; threshold-count = <6>; }; @@ -272,7 +271,6 @@ clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 3>; vref-mv = <3300>; channel-count = <26>; - threshold-reg-offset = <0x80>; threshold-count = <6>; status = "disabled"; }; diff --git a/dts/arm/nuvoton/npcx/npcx7.dtsi b/dts/arm/nuvoton/npcx/npcx7.dtsi index cad37d8ca66..529d5bdef35 100644 --- a/dts/arm/nuvoton/npcx/npcx7.dtsi +++ b/dts/arm/nuvoton/npcx/npcx7.dtsi @@ -237,7 +237,6 @@ /* ADC0 comparator configuration in npcx7 series */ adc0: adc@400d1000 { channel-count = <10>; - threshold-reg-offset = <0x14>; threshold-count = <3>; }; diff --git a/dts/arm/nuvoton/npcx/npcx9.dtsi b/dts/arm/nuvoton/npcx/npcx9.dtsi index 6561ba7b6dd..18a1278de57 100644 --- a/dts/arm/nuvoton/npcx/npcx9.dtsi +++ b/dts/arm/nuvoton/npcx/npcx9.dtsi @@ -258,7 +258,6 @@ /* ADC0 comparator configuration in npcx9 series */ adc0: adc@400d1000 { channel-count = <12>; - threshold-reg-offset = <0x60>; threshold-count = <6>; }; diff --git a/dts/bindings/adc/nuvoton,npcx-adc.yaml b/dts/bindings/adc/nuvoton,npcx-adc.yaml index 11c4d1c21dc..50d37d19d80 100644 --- a/dts/bindings/adc/nuvoton,npcx-adc.yaml +++ b/dts/bindings/adc/nuvoton,npcx-adc.yaml @@ -24,10 +24,6 @@ properties: type: int required: true description: the number of ADC channels - threshold-reg-offset: - type: int - required: true - description: the offset of threshold detector register address threshold-count: type: int required: true diff --git a/soc/arm/nuvoton_npcx/common/reg/reg_def.h b/soc/arm/nuvoton_npcx/common/reg/reg_def.h index 3f50d364950..794bb5545bb 100644 --- a/soc/arm/nuvoton_npcx/common/reg/reg_def.h +++ b/soc/arm/nuvoton_npcx/common/reg/reg_def.h @@ -581,12 +581,34 @@ struct adc_reg { volatile uint16_t MEAST; }; +/* ADC internal inline functions for multi-registers */ static inline uint32_t npcx_chndat_offset(uint32_t ch) { return 0x40 + ch * 2; } +static inline uint32_t npcx_thr_base(void) +{ + if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) { + return 0x014; + } else if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) { + return 0x060; + } else { /* NPCX4 and later series */ + return 0x080; + } +} + +static inline uint32_t npcx_thrctl_offset(uint32_t ctrl) +{ + return npcx_thr_base() + ctrl * 2; +} + #define CHNDAT(base, ch) (*(volatile uint16_t *)((base) + npcx_chndat_offset(ch))) +#define THRCTL(base, ctrl) \ + (*(volatile uint16_t *)(base + npcx_thrctl_offset(ctrl))) +#ifdef CONFIG_SOC_SERIES_NPCX4 +#define THEN(base) (*(volatile uint16_t *)(base + 0x90)) +#endif /* ADC register fields */ #define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)