From ea81b4b81264a0e8a29842923b54f9d290d84c50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 22 Dec 2021 11:28:16 +0100 Subject: [PATCH] drivers: display_nrf_led_matrix: Correct calculation of pixel period MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a follow-up to commit 4dfab40cac4c99eb28ef61dae0d5d1c062b5902f. The calculation of the pixel period is done incorrectly and results in higher than configured refresh frequency if pixels are refreshed in groups. Fix that and lower the base frequency for the timer and PWM so that wider range of refresh frequency can be used also with the pixel grouping. Signed-off-by: Andrzej Głąbek --- drivers/display/display_nrf_led_matrix.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/display/display_nrf_led_matrix.c b/drivers/display/display_nrf_led_matrix.c index 0d8bac33491..52b6dc4f70e 100644 --- a/drivers/display/display_nrf_led_matrix.c +++ b/drivers/display/display_nrf_led_matrix.c @@ -60,13 +60,15 @@ LOG_MODULE_REGISTER(nrf_led_matrix, CONFIG_DISPLAY_LOG_LEVEL); DT_FOREACH_PROP_ELEM(MATRIX_NODE, pixel_mapping, CHECK_PIXEL) #define REFRESH_FREQUENCY DT_PROP(MATRIX_NODE, refresh_frequency) -#define BASE_FREQUENCY 16000000 -#define TIMER_CLK_CONFIG NRF_TIMER_FREQ_16MHz -#define PWM_CLK_CONFIG NRF_PWM_CLK_16MHz +#define BASE_FREQUENCY 8000000 +#define TIMER_CLK_CONFIG NRF_TIMER_FREQ_8MHz +#define PWM_CLK_CONFIG NRF_PWM_CLK_8MHz #define BRIGHTNESS_MAX 255 -#define QUANTUM (BASE_FREQUENCY / (REFRESH_FREQUENCY * BRIGHTNESS_MAX * \ - PIXEL_COUNT * GROUP_SIZE)) +/* Always round up, as even a partially filled group uses the full time slot. */ +#define PIXEL_SLOTS (ROW_COUNT * NRFX_CEIL_DIV(COL_COUNT, GROUP_SIZE)) +#define QUANTUM (BASE_FREQUENCY \ + / (REFRESH_FREQUENCY * PIXEL_SLOTS * BRIGHTNESS_MAX)) #define PIXEL_PERIOD (BRIGHTNESS_MAX * QUANTUM) #if (PIXEL_PERIOD > BIT_MASK(16)) || \ (USE_PWM && PIXEL_PERIOD > PWM_COUNTERTOP_COUNTERTOP_Msk)