ARC: nSIM: Make reorganization of board and SoC structure

Change source tree organization for Synopsys nSIM platform.
Classical ARC architectures arc_v2 arc_v3 moved to arc_classic
SoC and boards family.
nSIM SoCs were separated regarding series: EM, HS, SEM, VPX2.
This PR sould be seeing as the preparation for
addition new nSIM platform based on the RISC-V architecture.

Signed-off-by: Nikolay Agishev <agishev@synopsys.com>

soc/snps/nsim/CMakeLists.txt

@@ -1,109 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-if(COMPILER STREQUAL gcc)
-  # GNU compiler options
-  zephyr_compile_options(-mcpu=${GCC_M_CPU})
-  if(CONFIG_ISA_ARCV2)
-    # ISA_ARCV2 & 32BIT
-    zephyr_compile_options(-mno-sdata)
-    zephyr_compile_options_ifdef(CONFIG_CPU_ARCEM -mmpy-option=wlh1)
-    zephyr_compile_options_ifdef(CONFIG_CPU_ARCHS -mmpy-option=plus_qmacw)
-    if(CONFIG_CPU_ARCHS)
-      zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all)
-    else()
-      zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
-    endif()
-  endif()
-
-  if(CONFIG_SOC_NSIM_VPX5)
-    message(FATAL_ERROR "ARC VPX targets can be built with ARC MWDT toolchain only")
-  endif()
-else()
-  # MWDT compiler options
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM -arcv2em -core3 -Xdiv_rem=radix2
-			       -Xmpy_option=mpyd -Xbitscan -Xswap -Xbarrel_shifter
-			       -Xshift_assist -Xdsp2 -Xdsp_complex
-			       -Xdsp_divsqrt=radix2 -Xdsp_itu -Xdsp_accshift=full
-			       -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
-			       -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM11D -arcv2em -core3 -Xdiv_rem=radix2
-			       -Xbitscan -Xswap -Xbarrel_shifter
-			       -Xshift_assist -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
-			       -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
-
-  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_EM11D -Hlib=em9d_nrg_fpusp -Hdsplib)
-
-  if(CONFIG_SOC_NSIM_EM11D)
-    set_property(GLOBAL PROPERTY z_arc_dsp_options -Xxy -Xagu_large -Hfxapi -Xdsp2
-              -Xdsp_accshift=full -Xdsp_divsqrt=radix2 -Xdsp_complex -Xdsp_itu
-              -Xdsp_ctrl=postshift,noguard,convergent -Xmpy_option=mpyd)
-  endif()
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_SEM -arcv2em -core3 -Xcode_density
-			       -Xdiv_rem=radix2 -Xswap -Xbitscan -Xmpy_option=mpyd
-			       -Xshift_assist -Xbarrel_shifter -Xdsp2
-			       -Xdsp_complex -Xdsp_divsqrt=radix2
-			       -Xdsp_accshift=limited -Xtimer0 -Xtimer1
-			       -Xsec_timer0 -Xstack_check -Xsec_modes -Xdmac)
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS -arcv2hs -core2 -Xatomic
-			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
-			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
-			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
-			       -Xtimer0 -Xtimer1)
-
-  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS -Hlib=hs38_full)
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_SMP -arcv2hs -core2 -Xatomic
-			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
-			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
-			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
-			       -Xtimer0 -Xtimer1)
-
-  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_SMP -Hlib=hs38_full)
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -arcv2hs -core2 -Xatomic
-			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
-			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
-			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
-			       -Xtimer0 -Xtimer1)
-
-  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -Hlib=hs38_full)
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_VPX5 -arcv2hs -core4 -uarch_rev=1:4 -Xcode_density
-             -HL -Xatomic -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh
-             -Xshift_assist -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a
-             -Hld_cycles=1 -DDCCM_SYSTEM_BASE_CORE0=0x80000000 -Hccm
-             -DICCM0_SYSTEM_BASE_CORE0=0x0000000 -Xstu=4 -Xvdsp4 -Xvec_unit_rev_minor=1
-             -Xvec_width=512 -Xvec_mem_size=256k -Xvec_mem_bank_width=16 -Xvec_max_fetch_size=16
-             -Xvec_num_slots=3 -Xvec_super_with_scalar -Xvec_regs=40 -Xvec_num_rd_ports=6
-             -Xvec_num_acc=8 -Xvec_num_mpy=2 -Xvec_mpy32 -Xvec_num_alu=3 -Xvec_guard_bit_option=2
-             -Xvec_stack_check -DVEC_MEM_SYS_BASE_CORE0=0xb4000000)
-
-  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_VPX5 -Hlib=vpx5_integer_full)
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
-			       -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
-			       -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
-
-  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X -Hlib=hs58_full)
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
-             -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
-             -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
-
-  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -Hlib=hs58_full)
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
-             -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
-
-  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X -Hlib=hs68_full_zephyr)
-
-  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
-             -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
-
-  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -Hlib=hs68_full_zephyr)
-endif()
-
-set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/snps/nsim/Kconfig

@@ -1,32 +0,0 @@
-# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_NSIM
-	select ARC
-
-config SOC_NSIM_EM
-	select CPU_HAS_MPU
-
-config SOC_NSIM_EM7D_V22
-	select CPU_HAS_MPU
-	select CPU_HAS_FPU
-
-config SOC_NSIM_EM11D
-	select CPU_HAS_MPU
-	select CPU_HAS_DSP
-
-config SOC_NSIM_SEM
-	select CPU_HAS_MPU
-	select CPU_HAS_FPU
-	select ARC_HAS_SECURE
-
-config SOC_NSIM_HS
-	select CPU_HAS_FPU
-	select CPU_HAS_MPU
-
-config SOC_NSIM_HS_SMP
-	select CPU_HAS_FPU
-
-config SOC_NSIM_HS_MPUV6
-	select CPU_HAS_MPU
-	select CPU_HAS_FPU

soc/snps/nsim/Kconfig.defconfig

@@ -1,11 +0,0 @@
-# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_NSIM
-
-config XIP
-	default n
-
-rsource "Kconfig.defconfig.*"
-
-endif # SOC_NSIM

soc/snps/nsim/Kconfig.soc

@@ -1,94 +0,0 @@
-# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_NSIM
-	bool
-
-config SOC_NSIM_EM
-	bool
-	select SOC_NSIM
-	help
-	  Synopsys ARC EM4 in nSIM
-
-config SOC_NSIM_EM7D_V22
-	bool
-	select SOC_NSIM
-	help
-	  Synopsys ARC EM7D_V22 in nSIM
-
-config SOC_NSIM_EM11D
-	bool
-	select SOC_NSIM
-	help
-	  Synopsys ARC EM11D in nSIM
-
-config SOC_NSIM_SEM
-	bool
-	select SOC_NSIM
-	help
-	  Synopsys ARC SEM in nSIM
-
-config SOC_NSIM_HS
-	bool
-	select SOC_NSIM
-	help
-	  Synopsys ARC HS3X in nSIM
-
-config SOC_NSIM_HS_SMP
-	bool
-	select SOC_NSIM
-	help
-	  Multi-core Synopsys ARC HS3X in nSIM
-
-config SOC_NSIM_HS_MPUV6
-	bool
-	select SOC_NSIM
-	help
-	  Synopsys ARC HS3X with MPU v6 in nSIM
-
-config SOC_NSIM_VPX5
-	bool
-	select SOC_NSIM
-	help
-	  Synopsys ARC VPX5 in nSIM
-
-config SOC_NSIM_HS5X
-	bool
-	select SOC_NSIM
-	help
-	  Synopsys ARC HS5x in nSIM
-
-config SOC_NSIM_HS5X_SMP
-	bool
-	select SOC_NSIM
-	help
-	  Multi-core Synopsys ARC HS5x in nSIM
-
-config SOC_NSIM_HS6X
-	bool
-	select SOC_NSIM
-	help
-	  Synopsys ARC HS6x in nSIM
-
-config SOC_NSIM_HS6X_SMP
-	bool
-	select SOC_NSIM
-	help
-	  Multi-core Synopsys ARC HS6x in nSIM
-
-config SOC
-	default "nsim_em" if SOC_NSIM_EM
-	default "nsim_em7d_v22" if SOC_NSIM_EM7D_V22
-	default "nsim_em11d" if SOC_NSIM_EM11D
-	default "nsim_sem" if SOC_NSIM_SEM
-	default "nsim_hs" if SOC_NSIM_HS
-	default "nsim_hs_smp" if SOC_NSIM_HS_SMP
-	default "nsim_hs_mpuv6" if SOC_NSIM_HS_MPUV6
-	default "nsim_vpx5" if SOC_NSIM_VPX5
-	default "nsim_hs5x" if SOC_NSIM_HS5X
-	default "nsim_hs5x_smp" if SOC_NSIM_HS5X_SMP
-	default "nsim_hs6x" if SOC_NSIM_HS6X
-	default "nsim_hs6x_smp" if SOC_NSIM_HS6X_SMP
-
-config SOC_SERIES
-	default "nsim" if SOC_NSIM

soc/snps/nsim/arc_classic/CMakeLists.txt

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+string(REPLACE "nsim_" "" NSIM_ARC_CLASSIC_SER "${SOC_SERIES}")
+add_subdirectory(${NSIM_ARC_CLASSIC_SER})
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/snps/nsim/arc_classic/Kconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_NSIM_ARC_CLASSIC
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_NSIM_ARC_CLASSIC

soc/snps/nsim/arc_classic/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_NSIM_ARC_CLASSIC
+
+config XIP
+	default n
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_NSIM_ARC_CLASSIC

soc/snps/nsim/arc_classic/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_NSIM_ARC_CLASSIC
+	bool
+
+config SOC_FAMILY
+	default "nsim_arc_classic" if SOC_FAMILY_NSIM_ARC_CLASSIC
+
+rsource "*/Kconfig.soc"

soc/snps/nsim/arc_classic/em/CMakeLists.txt

@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(COMPILER STREQUAL gcc)
+  # GNU compiler options
+  zephyr_compile_options(-mcpu=${GCC_M_CPU})
+
+  zephyr_compile_options(-mno-sdata)
+  zephyr_compile_options_ifdef(CONFIG_CPU_ARCEM -mmpy-option=wlh1)
+  zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
+
+else()
+  # MWDT compiler options
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM -arcv2em -core3 -Xdiv_rem=radix2
+			       -Xmpy_option=mpyd -Xbitscan -Xswap -Xbarrel_shifter
+			       -Xshift_assist -Xdsp2 -Xdsp_complex
+			       -Xdsp_divsqrt=radix2 -Xdsp_itu -Xdsp_accshift=full
+			       -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
+			       -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM11D -arcv2em -core3 -Xdiv_rem=radix2
+			       -Xbitscan -Xswap -Xbarrel_shifter
+			       -Xshift_assist -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
+			       -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_EM11D -Hlib=em9d_nrg_fpusp -Hdsplib)
+
+  if(CONFIG_SOC_NSIM_EM11D)
+    set_property(GLOBAL PROPERTY z_arc_dsp_options -Xxy -Xagu_large -Hfxapi -Xdsp2
+              -Xdsp_accshift=full -Xdsp_divsqrt=radix2 -Xdsp_complex -Xdsp_itu
+              -Xdsp_ctrl=postshift,noguard,convergent -Xmpy_option=mpyd)
+  endif()
+endif()

soc/snps/nsim/arc_classic/em/Kconfig

@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NSIM_EM
+	select ARC
+	select CPU_HAS_MPU

soc/snps/nsim/arc_classic/em/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NSIM_EM
+
+rsource "Kconfig.defconfig.em*"
+
+endif # SOC_SERIES_NSIM_EM

soc/snps/nsim/arc_classic/em/Kconfig.soc

@@ -0,0 +1,26 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NSIM_EM
+	bool
+	select SOC_FAMILY_NSIM_ARC_CLASSIC
+
+config SOC_SERIES
+	default "nsim_em" if SOC_SERIES_NSIM_EM
+
+config SOC_NSIM_EM
+	bool
+	select SOC_SERIES_NSIM_EM
+
+config SOC_NSIM_EM7D_V22
+	bool
+	select SOC_SERIES_NSIM_EM
+
+config SOC_NSIM_EM11D
+	bool
+	select SOC_SERIES_NSIM_EM
+
+config SOC
+	default "nsim_em" if SOC_NSIM_EM
+	default "nsim_em7d_v22" if SOC_NSIM_EM7D_V22
+	default "nsim_em11d" if SOC_NSIM_EM11D

soc/snps/nsim/arc_classic/hs/CMakeLists.txt

@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(COMPILER STREQUAL gcc)
+  # GNU compiler options
+  zephyr_compile_options(-mcpu=${GCC_M_CPU})
+
+  if(CONFIG_ISA_ARCV2)
+    # ISA_ARCV2 & 32BIT
+    zephyr_compile_options(-mno-sdata)
+    zephyr_compile_options_ifdef(CONFIG_CPU_ARCHS -mmpy-option=plus_qmacw)
+    zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all)
+  endif()
+else()
+  # MWDT compiler options
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS -arcv2hs -core2 -Xatomic
+			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
+			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
+			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
+			       -Xtimer0 -Xtimer1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS -Hlib=hs38_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_SMP -arcv2hs -core2 -Xatomic
+			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
+			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
+			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
+			       -Xtimer0 -Xtimer1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_SMP -Hlib=hs38_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -arcv2hs -core2 -Xatomic
+			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
+			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
+			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
+			       -Xtimer0 -Xtimer1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -Hlib=hs38_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
+			       -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
+			       -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X -Hlib=hs58_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
+             -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
+             -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -Hlib=hs58_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
+             -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X -Hlib=hs68_full_zephyr)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
+             -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -Hlib=hs68_full_zephyr)
+endif()

soc/snps/nsim/arc_classic/hs/Kconfig

@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NSIM_HS
+	select ARC
+	select CPU_HAS_FPU
+	select CPU_HAS_MPU if !SMP

soc/snps/nsim/arc_classic/hs/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NSIM_HS
+
+rsource "Kconfig.defconfig.hs*"
+
+endif # SOC_SERIES_NSIM_HS

soc/snps/nsim/arc_classic/hs/Kconfig.soc

@@ -0,0 +1,46 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NSIM_HS
+	bool
+	select SOC_FAMILY_NSIM_ARC_CLASSIC
+
+config SOC_SERIES
+	default "nsim_hs" if SOC_SERIES_NSIM_HS
+
+config SOC_NSIM_HS
+	bool
+	select SOC_SERIES_NSIM_HS
+
+config SOC_NSIM_HS_SMP
+	bool
+	select SOC_SERIES_NSIM_HS
+
+config SOC_NSIM_HS_MPUV6
+	bool
+	select SOC_SERIES_NSIM_HS
+
+config SOC_NSIM_HS5X
+	bool
+	select SOC_SERIES_NSIM_HS
+
+config SOC_NSIM_HS5X_SMP
+	bool
+	select SOC_SERIES_NSIM_HS
+
+config SOC_NSIM_HS6X
+	bool
+	select SOC_SERIES_NSIM_HS
+
+config SOC_NSIM_HS6X_SMP
+	bool
+	select SOC_SERIES_NSIM_HS
+
+config SOC
+	default "nsim_hs" if SOC_NSIM_HS
+	default "nsim_hs_smp" if SOC_NSIM_HS_SMP
+	default "nsim_hs_mpuv6" if SOC_NSIM_HS_MPUV6
+	default "nsim_hs5x" if SOC_NSIM_HS5X
+	default "nsim_hs5x_smp" if SOC_NSIM_HS5X_SMP
+	default "nsim_hs6x" if SOC_NSIM_HS6X
+	default "nsim_hs6x_smp" if SOC_NSIM_HS6X_SMP

soc/snps/nsim/arc_classic/sem/CMakeLists.txt

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(COMPILER STREQUAL gcc)
+  # GNU compiler options
+  zephyr_compile_options(-mcpu=${GCC_M_CPU})
+
+  # ISA_ARCV2 & 32BIT
+  zephyr_compile_options(-mno-sdata)
+  zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
+
+else()
+  # MWDT compiler options
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_SEM -arcv2em -core3 -Xcode_density
+			       -Xdiv_rem=radix2 -Xswap -Xbitscan -Xmpy_option=mpyd
+			       -Xshift_assist -Xbarrel_shifter -Xdsp2
+			       -Xdsp_complex -Xdsp_divsqrt=radix2
+			       -Xdsp_accshift=limited -Xtimer0 -Xtimer1
+			       -Xsec_timer0 -Xstack_check -Xsec_modes -Xdmac)
+
+endif()

soc/snps/nsim/arc_classic/sem/Kconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NSIM_SEM
+	select ARC
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU
+	select ARC_HAS_SECURE

soc/snps/nsim/arc_classic/sem/Kconfig.soc

@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NSIM_SEM
+	bool
+	select SOC_FAMILY_NSIM_ARC_CLASSIC
+
+config SOC_SERIES
+	default "nsim_sem" if SOC_SERIES_NSIM_SEM
+
+config SOC_NSIM_SEM
+	bool
+	select SOC_SERIES_NSIM_SEM
+
+config SOC
+	default "nsim_sem" if SOC_NSIM_SEM

soc/snps/nsim/arc_classic/soc.yml

@@ -0,0 +1,23 @@
+family:
+  - name: nsim_arc_classic
+    series:
+      - name: nsim_em
+        socs:
+          - name: nsim_em
+          - name: nsim_em7d_v22
+          - name: nsim_em11d
+      - name: nsim_hs
+        socs:
+          - name: nsim_hs
+          - name: nsim_hs_smp
+          - name: nsim_hs_mpuv6
+          - name: nsim_hs5x
+          - name: nsim_hs5x_smp
+          - name: nsim_hs6x
+          - name: nsim_hs6x_smp
+      - name: nsim_vpx
+        socs:
+          - name: nsim_vpx5
+      - name: nsim_sem
+        socs:
+          - name: nsim_sem

soc/snps/nsim/arc_classic/vpx5/CMakeLists.txt

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(COMPILER STREQUAL gcc)
+  # GNU compiler options
+
+  message(FATAL_ERROR "ARC VPX targets can be built with ARC MWDT toolchain only")
+
+else()
+  # MWDT compiler options
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_VPX5 -arcv2hs -core4 -uarch_rev=1:4 -Xcode_density
+             -HL -Xatomic -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh
+             -Xshift_assist -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a
+             -Hld_cycles=1 -DDCCM_SYSTEM_BASE_CORE0=0x80000000 -Hccm
+             -DICCM0_SYSTEM_BASE_CORE0=0x0000000 -Xstu=4 -Xvdsp4 -Xvec_unit_rev_minor=1
+             -Xvec_width=512 -Xvec_mem_size=256k -Xvec_mem_bank_width=16 -Xvec_max_fetch_size=16
+             -Xvec_num_slots=3 -Xvec_super_with_scalar -Xvec_regs=40 -Xvec_num_rd_ports=6
+             -Xvec_num_acc=8 -Xvec_num_mpy=2 -Xvec_mpy32 -Xvec_num_alu=3 -Xvec_guard_bit_option=2
+             -Xvec_stack_check -DVEC_MEM_SYS_BASE_CORE0=0xb4000000)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_VPX5 -Hlib=vpx5_integer_full)
+
+endif()

soc/snps/nsim/arc_classic/vpx5/Kconfig

@@ -0,0 +1,2 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0

soc/snps/nsim/arc_classic/vpx5/Kconfig.soc

@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NSIM_VPX5
+	bool
+	select SOC_FAMILY_NSIM_ARC_CLASSIC
+
+config SOC_SERIES
+	default "nsim_vpx5" if SOC_SERIES_NSIM_VPX5
+
+config SOC_NSIM_VPX5
+	bool
+	select SOC_SERIES_NSIM_VPX5
+	help
+	  Synopsys ARC VPX5 in nSIM
+
+config SOC
+	default "nsim_vpx5" if SOC_NSIM_VPX5

soc/snps/nsim/soc.yml

@@ -1,15 +0,0 @@
-series:
-- name: nsim
-  socs:
-  - name: nsim_em
-  - name: nsim_em7d_v22
-  - name: nsim_em11d
-  - name: nsim_hs
-  - name: nsim_hs_smp
-  - name: nsim_hs_mpuv6
-  - name: nsim_hs5x
-  - name: nsim_hs5x_smp
-  - name: nsim_hs6x
-  - name: nsim_hs6x_smp
-  - name: nsim_vpx5
-  - name: nsim_sem