From ea24dd40eb61065942f9577a69ea8b6defca209b Mon Sep 17 00:00:00 2001 From: Gerson Fernando Budke Date: Thu, 3 Aug 2023 12:57:38 +0200 Subject: [PATCH] soc: atmel: sam: Fix cache management The current platform initialization do not take in consideration cache management for historic reasons. This fixes any miss configuration and allow users to enable/disable caches at board definition. The default value is cache disabled and the below examples are for SAMV71 which have both I/D Cache available: I Cache only: CONFIG_CACHE_MANAGEMENT=y CONFIG_DCACHE=n D Cache only: CONFIG_CACHE_MANAGEMENT=y CONFIG_ICACHE=n I/D Cache disabled: CONFIG_ICACHE=n CONFIG_DCACHE=n I/D Cache Enabled: CONFIG_CACHE_MANAGEMENT=y Signed-off-by: Gerson Fernando Budke --- .../arm/sam_e70_xplained/sam_e70_xplained_defconfig | 1 + .../arm/sam_e70_xplained/sam_e70b_xplained_defconfig | 1 + boards/arm/sam_v71_xult/sam_v71_xult_defconfig | 1 + boards/arm/sam_v71_xult/sam_v71b_xult_defconfig | 1 + soc/arm/atmel_sam/same70/Kconfig.defconfig.series | 3 --- soc/arm/atmel_sam/same70/soc.c | 11 ++++++++--- soc/arm/atmel_sam/samv71/Kconfig.defconfig.series | 3 --- soc/arm/atmel_sam/samv71/soc.c | 11 ++++++++--- 8 files changed, 20 insertions(+), 12 deletions(-) diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig b/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig index ff191708aca..30cb50e4512 100644 --- a/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig +++ b/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_SAM_E70_XPLAINED=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y CONFIG_HW_STACK_PROTECTION=y CONFIG_WDT_DISABLE_AT_BOOT=y diff --git a/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig b/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig index e2c3583fb26..5aba40c4400 100644 --- a/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig +++ b/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_SAM_E70_XPLAINED=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y CONFIG_HW_STACK_PROTECTION=y CONFIG_WDT_DISABLE_AT_BOOT=y diff --git a/boards/arm/sam_v71_xult/sam_v71_xult_defconfig b/boards/arm/sam_v71_xult/sam_v71_xult_defconfig index 18f1a63e648..3c82428d40e 100644 --- a/boards/arm/sam_v71_xult/sam_v71_xult_defconfig +++ b/boards/arm/sam_v71_xult/sam_v71_xult_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_SAM_V71_XULT=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y CONFIG_HW_STACK_PROTECTION=y CONFIG_WDT_DISABLE_AT_BOOT=y diff --git a/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig b/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig index bd2a4ecec08..bf9eea03a5d 100644 --- a/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig +++ b/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_SAM_V71_XULT=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y CONFIG_HW_STACK_PROTECTION=y CONFIG_WDT_DISABLE_AT_BOOT=y diff --git a/soc/arm/atmel_sam/same70/Kconfig.defconfig.series b/soc/arm/atmel_sam/same70/Kconfig.defconfig.series index 3be4f1b59d8..f024e0d0616 100644 --- a/soc/arm/atmel_sam/same70/Kconfig.defconfig.series +++ b/soc/arm/atmel_sam/same70/Kconfig.defconfig.series @@ -38,7 +38,4 @@ config NUM_IRQS default 74 if SOC_ATMEL_SAME70_REVB default 71 -config CACHE_MANAGEMENT - default y - endif # SOC_SERIES_SAME70 diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c index 79b9c1a1ae8..a20632e6ede 100644 --- a/soc/arm/atmel_sam/same70/soc.c +++ b/soc/arm/atmel_sam/same70/soc.c @@ -226,10 +226,15 @@ static ALWAYS_INLINE void clock_init(void) void z_arm_platform_init(void) { - SCB_EnableICache(); - - if (!(SCB->CCR & SCB_CCR_DC_Msk)) { + if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) { + SCB_EnableICache(); + } else { + SCB_DisableICache(); + } + if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) { SCB_EnableDCache(); + } else { + SCB_DisableDCache(); } /* diff --git a/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series b/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series index f0db4faec2c..5209139f61c 100644 --- a/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series +++ b/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series @@ -38,7 +38,4 @@ config NUM_IRQS default 74 if SOC_ATMEL_SAMV71_REVB default 71 -config CACHE_MANAGEMENT - default y - endif # SOC_SERIES_SAMV71 diff --git a/soc/arm/atmel_sam/samv71/soc.c b/soc/arm/atmel_sam/samv71/soc.c index a805bc76a2b..53f4dfd3795 100644 --- a/soc/arm/atmel_sam/samv71/soc.c +++ b/soc/arm/atmel_sam/samv71/soc.c @@ -226,10 +226,15 @@ static ALWAYS_INLINE void clock_init(void) void z_arm_platform_init(void) { - SCB_EnableICache(); - - if (!(SCB->CCR & SCB_CCR_DC_Msk)) { + if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) { + SCB_EnableICache(); + } else { + SCB_DisableICache(); + } + if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) { SCB_EnableDCache(); + } else { + SCB_DisableDCache(); } /*