board: imx93_evk: enable ENET support for Cortex-A Core

Add ENET 1G support on Cortex-A Core, enable it in DTS.
Updated board document for supported features.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>

boards/nxp/imx93_evk/Kconfig.defconfig

@@ -0,0 +1,44 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_IMX93_EVK
+
+if BOARD_IMX93_EVK_MIMX9352_A55
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+config NET_TX_STACK_SIZE
+	default 8192
+
+config NET_RX_STACK_SIZE
+	default 8192
+
+if NET_TCP
+
+config NET_TCP_WORKQ_STACK_SIZE
+	default 8192
+
+endif # NET_TCP
+
+if NET_MGMT_EVENT
+
+config NET_MGMT_EVENT_STACK_SIZE
+	default 8192
+
+endif # NET_MGMT_EVENT
+
+if NET_SOCKETS_SERVICE
+
+config NET_SOCKETS_SERVICE_STACK_SIZE
+	default 8192
+
+endif # NET_SOCKETS_SERVICE
+
+endif # NETWORKING
+
+endif # BOARD_IMX93_EVK_MIMX9352_A55
+
+endif # BOARD_IMX93_EVK

boards/nxp/imx93_evk/doc/index.rst

@@ -48,8 +48,8 @@ Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core.
 Supported Features
 ==================
 
-The Zephyr mimx93_evk board configuration supports the following hardware
-features:
+The Zephyr mimx93_evk board Cortex-A Core configuration supports the following
+hardware features:
 
 +-----------+------------+-------------------------------------+
 | Interface | Controller | Driver/Component                    |
@@ -58,8 +58,18 @@ features:
 +-----------+------------+-------------------------------------+
 | ARM TIMER | on-chip    | system clock                        |
 +-----------+------------+-------------------------------------+
+| CLOCK     | on-chip    | clock_control                       |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
 | UART      | on-chip    | serial port                         |
 +-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | GPIO                                |
++-----------+------------+-------------------------------------+
+| TPM       | on-chip    | TPM Counter                         |
++-----------+------------+-------------------------------------+
+| ENET      | on-chip    | ethernet port                       |
++-----------+------------+-------------------------------------+
 
 Devices
 ========

boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, NXP
+ * Copyright 2022,2024 NXP
  * SPDX-License-Identifier: Apache-2.0
  *
  */
@@ -83,4 +83,41 @@
 		};
 	};
 
+	pinmux_mdio: pinmux_mdio {
+		group0 {
+			pinmux = <&iomuxc1_enet2_mdc_enet_mdc_enet1_mdc>,
+				<&iomuxc1_enet2_mdio_enet_mdio_enet1_mdio>;
+			bias-pull-down;
+			slew-rate = "slightly_fast";
+			drive-strength = "x6";
+		};
+	};
+
+	pinmux_enet: pinmux_enet {
+		group0 {
+			pinmux = <&iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
+				<&iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
+				<&iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
+				<&iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
+				<&iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>,
+				<&iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0>,
+				<&iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1>,
+				<&iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2>,
+				<&iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3>,
+				<&iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
+			bias-pull-down;
+			slew-rate = "slightly_fast";
+			drive-strength = "x6";
+		};
+
+		group1 {
+			pinmux = <&iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
+				<&iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc>;
+			bias-pull-down;
+			slew-rate = "fast";
+			drive-strength = "x6";
+		};
+
+	};
+
 };

boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts

@@ -66,6 +66,30 @@
 	};
 };
 
+&enet {
+	status = "okay";
+};
+
+&enet_mac {
+	pinctrl-0 = <&pinmux_enet>;
+	pinctrl-names = "default";
+	phy-handle = <&phy>;
+	zephyr,random-mac-address;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&enet_mdio {
+	pinctrl-0 = <&pinmux_mdio>;
+	pinctrl-names = "default";
+	status = "okay";
+	phy: phy@0 {
+		compatible = "realtek,rtl8211f";
+		reg = <2>;
+		status = "okay";
+	};
+};
+
 &lpuart1 {
 	status = "disabled";
 	current-speed = <115200>;

dts/arm64/nxp/nxp_mimx93_a55.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -348,6 +348,36 @@
 		status = "disabled";
 	};
 
+	enet: enet@42890000 {
+		compatible = "nxp,enet1g";
+		reg = <0x42890000 DT_SIZE_K(64)>;
+		clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
+		status = "disabled";
+
+		enet_mac: ethernet {
+			compatible = "nxp,enet-mac";
+			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "COMMON";
+			interrupt-parent = <&gic>;
+			nxp,mdio = <&enet_mdio>;
+			nxp,ptp-clock = <&enet_ptp_clock>;
+			status = "disabled";
+		};
+		enet_mdio: mdio {
+			compatible = "nxp,enet-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		enet_ptp_clock: ptp_clock {
+			compatible = "nxp,enet-ptp-clock";
+			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
+			status = "disabled";
+		};
+	};
+
 	tpm1: tpm@44310000 {
 		compatible = "nxp,tpm-timer";
 		reg = <0x44310000 DT_SIZE_K(64)>;

soc/nxp/imx/imx9/Kconfig

@@ -8,6 +8,7 @@ config SOC_MIMX9352_A55
 	select HAS_MCUX if CLOCK_CONTROL
 	select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL
 	select HAS_MCUX_IOMUXC if PINCTRL
+	select HAS_MCUX_CACHE
 
 config MCUX_CORE_SUFFIX
 	default "_ca55" if SOC_MIMX9352_A55