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board: imx93_evk: enable ENET support for Cortex-A Core

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Add ENET 1G support on Cortex-A Core, enable it in DTS.
Updated board document for supported features.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This commit is contained in:
Jiafei Pan 2024-06-21 17:30:01 +08:00 • committed by Anas Nashif
commit ea1a0a6950
6 changed files with 150 additions and 4 deletions
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44
boards/nxp/imx93_evk/Kconfig.defconfig Normal file
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@ -0,0 +1,44 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
if BOARD_IMX93_EVK
if BOARD_IMX93_EVK_MIMX9352_A55
if NETWORKING
config NET_L2_ETHERNET
default y
config NET_TX_STACK_SIZE
default 8192
config NET_RX_STACK_SIZE
default 8192
if NET_TCP
config NET_TCP_WORKQ_STACK_SIZE
default 8192
endif # NET_TCP
if NET_MGMT_EVENT
config NET_MGMT_EVENT_STACK_SIZE
default 8192
endif # NET_MGMT_EVENT
if NET_SOCKETS_SERVICE
config NET_SOCKETS_SERVICE_STACK_SIZE
default 8192
endif # NET_SOCKETS_SERVICE
endif # NETWORKING
endif # BOARD_IMX93_EVK_MIMX9352_A55
endif # BOARD_IMX93_EVK

14
boards/nxp/imx93_evk/doc/index.rst
View file

@ -48,8 +48,8 @@ Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core.
Supported Features
==================
The Zephyr mimx93_evk board configuration supports the following hardware
features:
The Zephyr mimx93_evk board Cortex-A Core configuration supports the following
hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
@ -58,8 +58,18 @@ features:
+-----------+------------+-------------------------------------+
| ARM TIMER | on-chip | system clock |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | GPIO |
+-----------+------------+-------------------------------------+
| TPM | on-chip | TPM Counter |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet port |
+-----------+------------+-------------------------------------+
Devices
========

39
boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, NXP
* Copyright 2022,2024 NXP
* SPDX-License-Identifier: Apache-2.0
*
*/
@ -83,4 +83,41 @@
};
};
pinmux_mdio: pinmux_mdio {
group0 {
pinmux = <&iomuxc1_enet2_mdc_enet_mdc_enet1_mdc>,
<&iomuxc1_enet2_mdio_enet_mdio_enet1_mdio>;
bias-pull-down;
slew-rate = "slightly_fast";
drive-strength = "x6";
};
};
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
<&iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
<&iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
<&iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
<&iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>,
<&iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0>,
<&iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1>,
<&iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2>,
<&iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3>,
<&iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
bias-pull-down;
slew-rate = "slightly_fast";
drive-strength = "x6";
};
group1 {
pinmux = <&iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
<&iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc>;
bias-pull-down;
slew-rate = "fast";
drive-strength = "x6";
};
};
};

24
boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts
View file

@ -66,6 +66,30 @@
};
};
&enet {
status = "okay";
};
&enet_mac {
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rgmii";
status = "okay";
};
&enet_mdio {
pinctrl-0 = <&pinmux_mdio>;
pinctrl-names = "default";
status = "okay";
phy: phy@0 {
compatible = "realtek,rtl8211f";
reg = <2>;
status = "okay";
};
};
&lpuart1 {
status = "disabled";
current-speed = <115200>;