doxygen: change comment style to match javadoc
The change replaces multiple asterisks to ** at the beginning of comments and adds a space before the asterisks at the beginning of lines. Change-Id: I7656bde3bf4d9a31e38941e43b580520432dabc1 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif
parent
20764a2e8d
commit
ea0d0b220c
305 changed files with 11249 additions and 11249 deletions
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@ -113,7 +113,7 @@ where to start a loop on these classes. Thus, a subsequent pci scan looking
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for class y will directly start at the relevant bus and device instead of
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restarting from 0.
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*/
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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@ -167,12 +167,12 @@ struct lookup_data {
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static struct bus_dev class_bd[PCI_CLASS_MAX] = {};
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static struct lookup_data __noinit lookup;
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/******************************************************************************
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*
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* pci_get_bar_config - return the configuration for the specified BAR
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*
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* RETURNS: 0 if BAR is implemented, -1 if not.
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*/
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/**
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*
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* pci_get_bar_config - return the configuration for the specified BAR
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*
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* RETURNS: 0 if BAR is implemented, -1 if not.
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*/
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static inline int pci_bar_config_get(union pci_addr_reg pci_ctrl_addr,
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uint32_t *config)
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@ -212,7 +212,7 @@ static inline int pci_bar_config_get(union pci_addr_reg pci_ctrl_addr,
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return -1;
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}
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/******************************************************************************
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/**
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*
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* pci_bar_params_get - retrieve the I/O address and IRQ of the specified BAR
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*
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@ -263,7 +263,7 @@ static inline int pci_bar_params_get(union pci_addr_reg pci_ctrl_addr,
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return 0;
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}
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/******************************************************************************
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/**
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*
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* pci_dev_scan - scan the specified PCI device for all sub functions
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*
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@ -374,7 +374,7 @@ void pci_bus_scan_init(void)
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lookup.bar = 0;
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}
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/******************************************************************************
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/**
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*
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* pci_bus_scan - scans PCI bus for devices
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*
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@ -428,7 +428,7 @@ int pci_bus_scan(struct pci_dev_info *dev_info)
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}
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#ifdef CONFIG_PCI_DEBUG
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/******************************************************************************
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/**
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*
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* pci_show - Show PCI device
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*
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@ -35,7 +35,7 @@ DESCRIPTION
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This module implements the PCI config space access functions
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*/
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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@ -52,18 +52,18 @@ This module implements the PCI config space access functions
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} while (0)
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#endif
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/*******************************************************************************
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*
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* pci_config_out_long - write a 32bit data to pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number
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* @param func_no Function number
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* @param offset Offset into the configuration space.
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* @param data Data written to the offset.
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*
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* RETURNS: N/A
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*/
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/**
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*
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* pci_config_out_long - write a 32bit data to pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number
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* @param func_no Function number
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* @param offset Offset into the configuration space.
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* @param data Data written to the offset.
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*
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* RETURNS: N/A
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*/
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void pci_config_out_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint32_t data)
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{
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@ -82,18 +82,18 @@ void pci_config_out_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint32_t), data);
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}
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/*******************************************************************************
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*
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* pci_config_out_word - write a 16bit data to pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data written to the offset.
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*
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* RETURNS: N/A
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*/
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/**
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*
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* pci_config_out_word - write a 16bit data to pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data written to the offset.
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*
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* RETURNS: N/A
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*/
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void pci_config_out_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint16_t data)
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{
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@ -112,18 +112,18 @@ void pci_config_out_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint16_t), data);
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}
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/*******************************************************************************
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*
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* pci_config_out_byte - write a 8bit data to pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data written to the offset.
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*
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* RETURNS: N/A
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*/
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/**
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*
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* pci_config_out_byte - write a 8bit data to pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data written to the offset.
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*
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* RETURNS: N/A
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*/
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void pci_config_out_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint8_t data)
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{
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@ -142,19 +142,19 @@ void pci_config_out_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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pci_write(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint8_t), data);
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}
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/*******************************************************************************
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*
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* pci_config_in_long - read a 32bit data from pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data read from the offset.
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*
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* RETURNS: N/A
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*
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*/
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/**
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*
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* pci_config_in_long - read a 32bit data from pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data read from the offset.
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*
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* RETURNS: N/A
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*
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*/
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void pci_config_in_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint32_t *data)
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{
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@ -173,19 +173,19 @@ void pci_config_in_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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pci_read(DEFAULT_PCI_CONTROLLER, pci_addr, sizeof(uint32_t), data);
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}
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/*******************************************************************************
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*
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* pci_config_in_word - read in a 16bit data from a pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data read from the offset.
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*
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* RETURNS: N/A
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*
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*/
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/**
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*
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* pci_config_in_word - read in a 16bit data from a pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data read from the offset.
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*
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* RETURNS: N/A
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*
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*/
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void pci_config_in_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint16_t *data)
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@ -210,19 +210,19 @@ void pci_config_in_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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*data = (uint16_t)pci_data;
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}
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/*******************************************************************************
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*
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* pci_config_in_byte - read in a 8bit data from a pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data read from the offset.
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*
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* RETURNS: N/A
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*
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*/
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/**
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*
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* pci_config_in_byte - read in a 8bit data from a pci reg in offset
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*
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* @param bus_no Bus number.
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* @param device_no Device number.
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* @param func_no Function number.
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* @param offset Offset into the configuration space.
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* @param data Data read from the offset.
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*
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* RETURNS: N/A
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*
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*/
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void pci_config_in_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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uint32_t offset, uint8_t *data)
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@ -247,23 +247,23 @@ void pci_config_in_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
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*data = (uint8_t)pci_data;
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}
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/*******************************************************************************
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*
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* pci_config_ext_cap_ptr_find - find extended capability in ECP linked list
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*
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* This routine searches for an extended capability in the linked list of
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* capabilities in config space. If found, the offset of the first byte
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* of the capability of interest in config space is returned via pOffset.
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*
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* @param ext_cap_find_id Extended capabilities ID to search for.
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* @param bus PCI bus number.
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* @param device PCI device number.
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* @param function PCI function number.
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* @param p_offset Returned config space offset.
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*
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* RETURNS: 0 if Extended Capability found, -1 otherwise
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*
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*/
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/**
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*
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* pci_config_ext_cap_ptr_find - find extended capability in ECP linked list
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*
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* This routine searches for an extended capability in the linked list of
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* capabilities in config space. If found, the offset of the first byte
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* of the capability of interest in config space is returned via pOffset.
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*
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* @param ext_cap_find_id Extended capabilities ID to search for.
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* @param bus PCI bus number.
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* @param device PCI device number.
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* @param function PCI function number.
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* @param p_offset Returned config space offset.
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*
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* RETURNS: 0 if Extended Capability found, -1 otherwise
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*
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*/
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int pci_config_ext_cap_ptr_find(uint8_t ext_cap_find_id, uint32_t bus,
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uint32_t device, uint32_t function,
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@ -35,7 +35,7 @@ DESCRIPTION
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This module implements the PCI H/W access functions.
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*/
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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@ -52,16 +52,16 @@ This module implements the PCI H/W access functions.
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#error "PCI_CTRL_DATA_REG cannot be zero"
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#endif
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/******************************************************************************
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*
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* pci_ctrl_read - read a PCI controller register
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*
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* This routine reads the specified register from the PCI controller and
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* places the data into the provided buffer.
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*
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* RETURNS: N/A
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*
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*/
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/**
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*
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* pci_ctrl_read - read a PCI controller register
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*
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* This routine reads the specified register from the PCI controller and
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* places the data into the provided buffer.
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*
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* RETURNS: N/A
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*
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*/
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static void pci_ctrl_read(uint32_t reg, /* PCI register to read */
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uint32_t *data, /* where to put the data */
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@ -86,16 +86,16 @@ static void pci_ctrl_read(uint32_t reg, /* PCI register to read */
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}
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}
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/******************************************************************************
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*
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* pci_ctrl_write - write a PCI controller register
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*
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* This routine writes the provided data to the specified register in the PCI
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* controller.
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*
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* RETURNS: N/A
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*
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*/
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/**
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*
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* pci_ctrl_write - write a PCI controller register
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*
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* This routine writes the provided data to the specified register in the PCI
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* controller.
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*
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* RETURNS: N/A
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*
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*/
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static void pci_ctrl_write(uint32_t reg, /* PCI register to write */
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uint32_t data, /* data to write */
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@ -121,15 +121,15 @@ static void pci_ctrl_write(uint32_t reg, /* PCI register to write */
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}
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}
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/******************************************************************************
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*
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* pci_ctrl_data_read - read the PCI controller data register
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*
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* This routine reads the data register of the specified PCI controller.
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*
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* RETURNS: 0 or -1
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*
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*/
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/**
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*
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* pci_ctrl_data_read - read the PCI controller data register
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*
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* This routine reads the data register of the specified PCI controller.
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*
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* RETURNS: 0 or -1
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*
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*/
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static int pci_ctrl_data_read(uint32_t controller, /* controller number */
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uint32_t offset, /* offset within data region */
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@ -147,16 +147,16 @@ static int pci_ctrl_data_read(uint32_t controller, /* controller number */
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return 0;
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}
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/******************************************************************************
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*
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* pci_ctrl_data_write - write the PCI controller data register
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*
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* This routine writes the provided data to the data register of the
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* specified PCI controller.
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*
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* RETURNS: 0 or -1
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*
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*/
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/**
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*
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* pci_ctrl_data_write - write the PCI controller data register
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*
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* This routine writes the provided data to the data register of the
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* specified PCI controller.
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*
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* RETURNS: 0 or -1
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*
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*/
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static int pci_ctrl_data_write(uint32_t controller, /* controller number */
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uint32_t offset, /* offset within address register */
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@ -174,16 +174,16 @@ static int pci_ctrl_data_write(uint32_t controller, /* controller number */
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return 0;
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}
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/******************************************************************************
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*
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* pci_ctrl_addr_write - write the PCI controller address register
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*
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* This routine writes the provided data to the address register of the
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* specified PCI controller.
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*
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* RETURNS: 0 or -1
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*
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*/
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/**
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*
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* pci_ctrl_addr_write - write the PCI controller address register
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*
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* This routine writes the provided data to the address register of the
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* specified PCI controller.
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*
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* RETURNS: 0 or -1
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*
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*/
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static int pci_ctrl_addr_write(uint32_t controller, /* controller number */
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uint32_t offset, /* offset within address register */
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@ -200,52 +200,52 @@ static int pci_ctrl_addr_write(uint32_t controller, /* controller number */
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return 0;
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}
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/*******************************************************************************
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*
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* pci_read - read a PCI register from a device
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*
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* This routine reads data from a PCI device's configuration space. The
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* device and register to read is specified by the address parameter ("addr")
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* and must be set appropriately by the caller. The address is defined by
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* the structure type pci_addr_t and contains the following members:
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*
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* bus: PCI bus number (0-255)
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* device: PCI device number (0-31)
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* func: device function number (0-7)
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* reg: device 32-bit register number to read (0-63)
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* offset: offset within 32-bit register to read (0-3)
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*
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* The size parameter specifies the number of bytes to read from the PCI
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* configuration space, valid values are 1, 2, and 4 bytes. A 32-bit value
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* is always returned but it will contain only the number of bytes specified
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* by the size parameter.
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*
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* If multiple PCI controllers are present in the system, the controller id
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* can be specified in the "controller" parameter. If only one controller
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* is present, the id DEFAULT_PCI_CONTROLLER can be used to denote this
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* controller.
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*
|
||||
* Example:
|
||||
*
|
||||
* union pci_addr_reg addr;
|
||||
* uint32_t status;
|
||||
*
|
||||
* addr.field.bus = 0; /@ PCI bus zero @/
|
||||
* addr.field.device = 1; /@ PCI device one @/
|
||||
* addr.field.func = 0; /@ PCI function zero @/
|
||||
* addr.field.reg = 4; /@ PCI register 4 @/
|
||||
* addr.field.offset = 0; /@ PCI register offset @/
|
||||
*
|
||||
* pci_read (DEFAULT_PCI_CONTROLLER, addr, sizeof(uint16_t), &status);
|
||||
*
|
||||
*
|
||||
* NOTE:
|
||||
* Reading of PCI data must be performed as an atomic operation. It is up to
|
||||
* the caller to enforce this.
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*
|
||||
*/
|
||||
/**
|
||||
*
|
||||
* pci_read - read a PCI register from a device
|
||||
*
|
||||
* This routine reads data from a PCI device's configuration space. The
|
||||
* device and register to read is specified by the address parameter ("addr")
|
||||
* and must be set appropriately by the caller. The address is defined by
|
||||
* the structure type pci_addr_t and contains the following members:
|
||||
*
|
||||
* bus: PCI bus number (0-255)
|
||||
* device: PCI device number (0-31)
|
||||
* func: device function number (0-7)
|
||||
* reg: device 32-bit register number to read (0-63)
|
||||
* offset: offset within 32-bit register to read (0-3)
|
||||
*
|
||||
* The size parameter specifies the number of bytes to read from the PCI
|
||||
* configuration space, valid values are 1, 2, and 4 bytes. A 32-bit value
|
||||
* is always returned but it will contain only the number of bytes specified
|
||||
* by the size parameter.
|
||||
*
|
||||
* If multiple PCI controllers are present in the system, the controller id
|
||||
* can be specified in the "controller" parameter. If only one controller
|
||||
* is present, the id DEFAULT_PCI_CONTROLLER can be used to denote this
|
||||
* controller.
|
||||
*
|
||||
* Example:
|
||||
*
|
||||
* union pci_addr_reg addr;
|
||||
* uint32_t status;
|
||||
*
|
||||
* addr.field.bus = 0; /@ PCI bus zero @/
|
||||
* addr.field.device = 1; /@ PCI device one @/
|
||||
* addr.field.func = 0; /@ PCI function zero @/
|
||||
* addr.field.reg = 4; /@ PCI register 4 @/
|
||||
* addr.field.offset = 0; /@ PCI register offset @/
|
||||
*
|
||||
* pci_read (DEFAULT_PCI_CONTROLLER, addr, sizeof(uint16_t), &status);
|
||||
*
|
||||
*
|
||||
* NOTE:
|
||||
* Reading of PCI data must be performed as an atomic operation. It is up to
|
||||
* the caller to enforce this.
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*
|
||||
*/
|
||||
|
||||
void pci_read(uint32_t controller, /* PCI controller to use */
|
||||
union pci_addr_reg addr, /* PCI address to read */
|
||||
|
|
@ -290,52 +290,52 @@ void pci_read(uint32_t controller, /* PCI controller to use */
|
|||
pci_ctrl_data_read(controller, access_offset, data, access_size);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* pci_write - write a to a PCI register
|
||||
*
|
||||
* This routine writes data to a PCI device's configuration space. The
|
||||
* device and register to write is specified by the address parameter ("addr")
|
||||
* and must be set appropriately by the caller. The address is defined by
|
||||
* the structure type pci_addr_t and contains the following members:
|
||||
*
|
||||
* bus: PCI bus number (0-255)
|
||||
* device: PCI device number (0-31)
|
||||
* func: device function number (0-7)
|
||||
* reg: device register number to read (0-63)
|
||||
* offset: offset within 32-bit register to write (0-3)
|
||||
*
|
||||
* The size parameter specifies the number of bytes to write to the PCI
|
||||
* configuration space, valid values are 1, 2, and 4 bytes. A 32-bit value
|
||||
* is always provided but only the number of bytes specified by the size
|
||||
* parameter will be written to the device.
|
||||
*
|
||||
* If multiple PCI controllers are present in the system, the controller id
|
||||
* can be specified in the "controller" parameter. If only one controller
|
||||
* is present, the id DEFAULT_PCI_CONTROLLER can be used to denote this
|
||||
* controller.
|
||||
*
|
||||
* Example:
|
||||
*
|
||||
* pci_addr_t addr;
|
||||
* uint32_t bar0 = 0xE0000000;
|
||||
*
|
||||
* addr.field.bus = 0; /@ PCI bus zero @/
|
||||
* addr.field.device = 1; /@ PCI device one @/
|
||||
* addr.field.func = 0; /@ PCI function zero @/
|
||||
* addr.field.reg = 16; /@ PCI register 16 @/
|
||||
* addr.field.offset = 0; /@ PCI register offset @/
|
||||
*
|
||||
* pci_write (DEFAULT_PCI_CONTROLLER, addr, sizeof(uint32_t), bar0);
|
||||
*
|
||||
* NOTE:
|
||||
* Writing of PCI data must be performed as an atomic operation. It is up to
|
||||
* the caller to enforce this.
|
||||
*
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*
|
||||
*/
|
||||
/**
|
||||
*
|
||||
* pci_write - write a to a PCI register
|
||||
*
|
||||
* This routine writes data to a PCI device's configuration space. The
|
||||
* device and register to write is specified by the address parameter ("addr")
|
||||
* and must be set appropriately by the caller. The address is defined by
|
||||
* the structure type pci_addr_t and contains the following members:
|
||||
*
|
||||
* bus: PCI bus number (0-255)
|
||||
* device: PCI device number (0-31)
|
||||
* func: device function number (0-7)
|
||||
* reg: device register number to read (0-63)
|
||||
* offset: offset within 32-bit register to write (0-3)
|
||||
*
|
||||
* The size parameter specifies the number of bytes to write to the PCI
|
||||
* configuration space, valid values are 1, 2, and 4 bytes. A 32-bit value
|
||||
* is always provided but only the number of bytes specified by the size
|
||||
* parameter will be written to the device.
|
||||
*
|
||||
* If multiple PCI controllers are present in the system, the controller id
|
||||
* can be specified in the "controller" parameter. If only one controller
|
||||
* is present, the id DEFAULT_PCI_CONTROLLER can be used to denote this
|
||||
* controller.
|
||||
*
|
||||
* Example:
|
||||
*
|
||||
* pci_addr_t addr;
|
||||
* uint32_t bar0 = 0xE0000000;
|
||||
*
|
||||
* addr.field.bus = 0; /@ PCI bus zero @/
|
||||
* addr.field.device = 1; /@ PCI device one @/
|
||||
* addr.field.func = 0; /@ PCI function zero @/
|
||||
* addr.field.reg = 16; /@ PCI register 16 @/
|
||||
* addr.field.offset = 0; /@ PCI register offset @/
|
||||
*
|
||||
* pci_write (DEFAULT_PCI_CONTROLLER, addr, sizeof(uint32_t), bar0);
|
||||
*
|
||||
* NOTE:
|
||||
* Writing of PCI data must be performed as an atomic operation. It is up to
|
||||
* the caller to enforce this.
|
||||
*
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*
|
||||
*/
|
||||
|
||||
void pci_write(uint32_t controller, /* controller to use */
|
||||
union pci_addr_reg addr, /* PCI address to read */
|
||||
|
|
@ -379,15 +379,15 @@ void pci_write(uint32_t controller, /* controller to use */
|
|||
pci_ctrl_data_write(controller, access_offset, data, access_size);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* pci_header_get - get the PCI header for a device
|
||||
*
|
||||
* This routine reads the PCI header for the specified device and puts the
|
||||
* result in the supplied header structure.
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*/
|
||||
/**
|
||||
*
|
||||
* pci_header_get - get the PCI header for a device
|
||||
*
|
||||
* This routine reads the PCI header for the specified device and puts the
|
||||
* result in the supplied header structure.
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*/
|
||||
|
||||
void pci_header_get(uint32_t controller,
|
||||
union pci_addr_reg pci_ctrl_addr,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue