gpio: nxp_s32: prepare to support multiple interrupt controllers
Refactor external interrupts infrastructure to prepare supporting multiple interrupt controllers. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles
Fabio Baltieri
parent
c8a5cf6728
commit
ea08227dd0
1 changed files with 88 additions and 77 deletions
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@ -9,20 +9,27 @@
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/logging/log.h>
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#include <Siul2_Port_Ip.h>
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#include <Siul2_Dio_Ip.h>
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LOG_MODULE_REGISTER(nxp_s32_gpio, CONFIG_GPIO_LOG_LEVEL);
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#ifdef CONFIG_NXP_S32_EIRQ
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#include <zephyr/drivers/interrupt_controller/intc_eirq_nxp_s32.h>
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struct eirq_nxp_s32_info {
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const struct device *eirq_dev;
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uint8_t num_lines;
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struct gpio_pin_line {
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uint8_t pin;
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uint8_t line;
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} gpio_pin_lines[];
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#define NXP_S32_GPIO_LINE_NOT_FOUND 0xff
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struct gpio_nxp_s32_irq_map {
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uint8_t pin;
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uint8_t line;
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} __packed;
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struct gpio_nxp_s32_irq_config {
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const struct device *ctrl;
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uint8_t map_cnt;
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struct gpio_nxp_s32_irq_map *map;
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};
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#endif
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@ -34,7 +41,7 @@ struct gpio_nxp_s32_config {
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Siul2_Port_Ip_PortType *port_base;
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#ifdef CONFIG_NXP_S32_EIRQ
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struct eirq_nxp_s32_info *eirq_info;
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struct gpio_nxp_s32_irq_config *eirq_info;
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#endif
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};
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@ -155,17 +162,26 @@ static int nxp_s32_gpio_port_toggle_bits(const struct device *port,
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#ifdef CONFIG_NXP_S32_EIRQ
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static uint8_t nxp_s32_gpio_pin_to_line(const struct eirq_nxp_s32_info *eirq_info, uint8_t pin)
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static uint8_t nxp_s32_gpio_pin_to_line(const struct gpio_nxp_s32_irq_config *irq_cfg,
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uint8_t pin)
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{
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uint8_t i;
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for (i = 0; i < eirq_info->num_lines; i++) {
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if (eirq_info->gpio_pin_lines[i].pin == pin) {
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return eirq_info->gpio_pin_lines[i].line;
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for (i = 0; i < irq_cfg->map_cnt; i++) {
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if (irq_cfg->map[i].pin == pin) {
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return irq_cfg->map[i].line;
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}
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}
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return SIUL2_ICU_IP_NUM_OF_CHANNELS;
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return NXP_S32_GPIO_LINE_NOT_FOUND;
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}
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static void nxp_s32_gpio_isr(uint8_t pin, void *arg)
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{
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const struct device *dev = (struct device *)arg;
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struct gpio_nxp_s32_data *data = dev->data;
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gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
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}
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static int nxp_s32_gpio_eirq_get_trigger(Siul2_Icu_Ip_EdgeType *edge_type,
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@ -198,12 +214,48 @@ static int nxp_s32_gpio_eirq_get_trigger(Siul2_Icu_Ip_EdgeType *edge_type,
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return 0;
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}
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static void nxp_s32_gpio_isr(uint8_t pin, void *arg)
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static int nxp_s32_gpio_config_eirq(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct device *dev = (struct device *)arg;
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struct gpio_nxp_s32_data *data = dev->data;
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const struct gpio_nxp_s32_config *config = dev->config;
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const struct gpio_nxp_s32_irq_config *irq_cfg = config->eirq_info;
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uint8_t irq_line;
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Siul2_Icu_Ip_EdgeType edge_type;
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gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
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if (irq_cfg == NULL) {
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LOG_ERR("external interrupt controller not available or enabled");
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return -ENOTSUP;
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}
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if (nxp_s32_gpio_eirq_get_trigger(&edge_type, mode, trig)) {
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LOG_ERR("trigger or mode not supported");
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return -ENOTSUP;
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}
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irq_line = nxp_s32_gpio_pin_to_line(irq_cfg, pin);
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if (irq_line == NXP_S32_GPIO_LINE_NOT_FOUND) {
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if (edge_type == SIUL2_ICU_DISABLE) {
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return 0;
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}
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LOG_ERR("pin %d cannot be used for external interrupt", pin);
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return -ENOTSUP;
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}
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if (edge_type == SIUL2_ICU_DISABLE) {
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eirq_nxp_s32_disable_interrupt(irq_cfg->ctrl, irq_line);
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eirq_nxp_s32_unset_callback(irq_cfg->ctrl, irq_line);
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} else {
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if (eirq_nxp_s32_set_callback(irq_cfg->ctrl, irq_line,
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nxp_s32_gpio_isr, pin, (void *)dev)) {
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LOG_ERR("pin %d is already in use", pin);
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return -EBUSY;
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}
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eirq_nxp_s32_enable_interrupt(irq_cfg->ctrl, irq_line, edge_type);
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}
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return 0;
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}
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static int nxp_s32_gpio_pin_interrupt_configure(const struct device *dev,
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@ -211,48 +263,7 @@ static int nxp_s32_gpio_pin_interrupt_configure(const struct device *dev,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_nxp_s32_config *config = dev->config;
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const struct eirq_nxp_s32_info *eirq_info = config->eirq_info;
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uint8_t eirq_line;
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Siul2_Icu_Ip_EdgeType edge_type;
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if (eirq_info == NULL) {
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/*
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* There is no external interrupt device for
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* the GPIO port or exists but is not enabled
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*/
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return -ENOTSUP;
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}
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eirq_line = nxp_s32_gpio_pin_to_line(eirq_info, pin);
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if (eirq_line == SIUL2_ICU_IP_NUM_OF_CHANNELS) {
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/*
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* GPIO pin cannot be used for processing
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* external interrupt signal
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*/
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return -ENOTSUP;
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}
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if (nxp_s32_gpio_eirq_get_trigger(&edge_type, mode, trig)) {
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return -ENOTSUP;
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}
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if (edge_type == SIUL2_ICU_DISABLE) {
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eirq_nxp_s32_disable_interrupt(eirq_info->eirq_dev, eirq_line);
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eirq_nxp_s32_unset_callback(eirq_info->eirq_dev, eirq_line);
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} else {
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if (eirq_nxp_s32_set_callback(eirq_info->eirq_dev, eirq_line,
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nxp_s32_gpio_isr, pin, (void *)dev)) {
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return -EBUSY;
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}
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eirq_nxp_s32_enable_interrupt(eirq_info->eirq_dev, eirq_line, edge_type);
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}
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return 0;
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return nxp_s32_gpio_config_eirq(dev, pin, mode, trig);
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}
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static int nxp_s32_gpio_manage_callback(const struct device *dev,
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@ -266,7 +277,7 @@ static int nxp_s32_gpio_manage_callback(const struct device *dev,
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static uint32_t nxp_s32_gpio_get_pending_int(const struct device *dev)
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{
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const struct gpio_nxp_s32_config *config = dev->config;
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const struct eirq_nxp_s32_info *eirq_info = config->eirq_info;
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const struct gpio_nxp_s32_irq_config *eirq_info = config->eirq_info;
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if (eirq_info == NULL) {
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/*
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@ -280,7 +291,7 @@ static uint32_t nxp_s32_gpio_get_pending_int(const struct device *dev)
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* Return all pending lines of the interrupt controller
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* that GPIO port belongs to
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*/
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return eirq_nxp_s32_get_pending(eirq_info->eirq_dev);
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return eirq_nxp_s32_get_pending(eirq_info->ctrl);
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}
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#endif /* CONFIG_NXP_S32_EIRQ */
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@ -424,30 +435,30 @@ static const struct gpio_driver_api gpio_nxp_s32_driver_api = {
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DT_INST_PHANDLE(n, interrupt_parent)
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#define GPIO_NXP_S32_EIRQ_PIN_LINE(idx, n) \
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{ \
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.pin = DT_INST_IRQ_BY_IDX(n, idx, gpio_pin), \
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.line = DT_INST_IRQ_BY_IDX(n, idx, eirq_line), \
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}
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DT_INST_IRQ_BY_IDX(n, idx, gpio_pin), \
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DT_INST_IRQ_BY_IDX(n, idx, eirq_line) \
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#define GPIO_NXP_S32_SET_EIRQ_INFO(n) \
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BUILD_ASSERT((DT_NODE_HAS_PROP(DT_DRV_INST(n), interrupt_parent) == \
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DT_NODE_HAS_PROP(DT_DRV_INST(n), interrupts)), \
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"interrupts and interrupt-parent must be set when" \
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" using external interrupts"); \
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IF_ENABLED(DT_NODE_HAS_STATUS(GPIO_NXP_S32_EIRQ_NODE(n), okay), \
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(static struct eirq_nxp_s32_info eirq_nxp_s32_info_##n = { \
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.eirq_dev = DEVICE_DT_GET(GPIO_NXP_S32_EIRQ_NODE(n)), \
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.gpio_pin_lines = { \
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LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), \
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GPIO_NXP_S32_EIRQ_PIN_LINE, (,), n) \
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}, \
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.num_lines = DT_NUM_IRQS(DT_DRV_INST(n)) \
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"interrupts and interrupt-parent must be set when " \
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"using external interrupts"); \
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IF_ENABLED(DT_NODE_HAS_STATUS(GPIO_NXP_S32_EIRQ_NODE(n), okay), ( \
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static uint8_t gpio_nxp_s32_eirq_data_##n[] = { \
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LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), \
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GPIO_NXP_S32_EIRQ_PIN_LINE, (,), n) \
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}; \
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))
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static struct gpio_nxp_s32_irq_config gpio_nxp_s32_eirq_##n = { \
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.ctrl = DEVICE_DT_GET(GPIO_NXP_S32_EIRQ_NODE(n)), \
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.map_cnt = DT_NUM_IRQS(DT_DRV_INST(n)), \
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.map = (struct gpio_nxp_s32_irq_map *) \
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gpio_nxp_s32_eirq_data_##n, \
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}; \
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))
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#define GPIO_NXP_S32_GET_EIRQ_INFO(n) \
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.eirq_info = UTIL_AND(DT_NODE_HAS_STATUS(GPIO_NXP_S32_EIRQ_NODE(n), okay),\
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&eirq_nxp_s32_info_##n)
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&gpio_nxp_s32_eirq_##n),
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#else
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#define GPIO_NXP_S32_SET_EIRQ_INFO(n)
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#define GPIO_NXP_S32_GET_EIRQ_INFO(n)
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