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soc: sam0: samd: Fix switching between clocks

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The clock z_arm_platform_init hangs switching between clocks when using
MCUboot. This fixes the issue using the 8MHz internal clock as gclk_main
source when configuring PLL/DFLL.

Fixes: #67220

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2024-01-05 19:34:34 +01:00 • committed by Henrik Brix Andersen
commit e9b26b5eb6
1 changed files with 17 additions and 4 deletions
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21
soc/arm/atmel_sam0/common/soc_samd2x.c
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@ -38,9 +38,6 @@
#define FUSES_OSC32K_CAL_Msk FUSES_OSC32KCAL_Msk #define FUSES_OSC32K_CAL_Msk FUSES_OSC32KCAL_Msk
#endif #endif
#if !CONFIG_SOC_ATMEL_SAMD_OSC8M || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
#define osc8m_init()
#else
static inline void osc8m_init(void) static inline void osc8m_init(void)
{ {
uint32_t reg; uint32_t reg;
@ -56,8 +53,24 @@ static inline void osc8m_init(void)
while (!SYSCTRL->PCLKSR.bit.OSC8MRDY) { while (!SYSCTRL->PCLKSR.bit.OSC8MRDY) {
} }
/* Use 8Mhz clock as gclk_main to allow switching between clocks
* when using bootloaders
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID(0)
| GCLK_GENDIV_DIV(0);
while (GCLK->STATUS.bit.SYNCBUSY) {
}
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0)
| GCLK_GENCTRL_SRC_OSC8M
| GCLK_GENCTRL_IDC
| GCLK_GENCTRL_GENEN;
while (GCLK->STATUS.bit.SYNCBUSY) {
}
} }
#endif
#if !CONFIG_SOC_ATMEL_SAMD_OSC32K || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN #if !CONFIG_SOC_ATMEL_SAMD_OSC32K || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
#define osc32k_init() #define osc32k_init()