diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt
index b4230c932ac..e8d06bc6011 100644
--- a/drivers/clock_control/CMakeLists.txt
+++ b/drivers/clock_control/CMakeLists.txt
@@ -11,5 +11,6 @@ if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X stm32f1x_ll_clock.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X stm32f3x_ll_clock.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X stm32f4x_ll_clock.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X stm32l0x_ll_clock.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X stm32l4x_ll_clock.c)
 endif()
diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32
index 803829826a6..94fa657d06f 100644
--- a/drivers/clock_control/Kconfig.stm32
+++ b/drivers/clock_control/Kconfig.stm32
@@ -247,6 +247,27 @@ config CLOCK_STM32_PLL_Q_DIVISOR
 
 endif # SOC_SERIES_STM32F4X
 
+if SOC_SERIES_STM32L0X
+
+config CLOCK_STM32_PLL_MULTIPLIER
+	int "PLL multiplier"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 4
+	range 3 48
+	help
+	 PLL multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48.
+	 PLL output must not exceed 96MHz(1.8V)/48MHz(1.5V)/24MHz(1.2V).
+
+config CLOCK_STM32_PLL_DIVISOR
+	int "PLL divisor"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 2
+	range 2 4
+	help
+	  PLL divisor, allowed values: 2-4.
+
+endif # SOC_SERIES_STM32L0X
+
 if SOC_SERIES_STM32L4X
 
 config CLOCK_STM32_PLL_M_DIVISOR
diff --git a/drivers/clock_control/stm32_ll_clock.c b/drivers/clock_control/stm32_ll_clock.c
index 71fa569a641..83285b35116 100644
--- a/drivers/clock_control/stm32_ll_clock.c
+++ b/drivers/clock_control/stm32_ll_clock.c
@@ -74,6 +74,11 @@ static inline int stm32_clock_control_on(struct device *dev,
 		LL_APB2_GRP1_EnableClock(pclken->enr);
 		break;
 #endif /* CONFIG_SOC_SERIES_STM32F0X */
+#ifdef CONFIG_SOC_SERIES_STM32L0X
+	case STM32_CLOCK_BUS_IOP:
+		LL_IOP_GRP1_EnableClock(pclken->enr);
+		break;
+#endif /* CONFIG_SOC_SERIES_STM32L0X */
 	}
 
 	return 0;
@@ -109,6 +114,11 @@ static inline int stm32_clock_control_off(struct device *dev,
 		LL_APB2_GRP1_DisableClock(pclken->enr);
 		break;
 #endif /* CONFIG_SOC_SERIES_STM32F0X */
+#ifdef CONFIG_SOC_SERIES_STM32L0X
+	case STM32_CLOCK_BUS_IOP:
+		LL_IOP_GRP1_DisableClock(pclken->enr);
+		break;
+#endif /* CONFIG_SOC_SERIES_STM32L0X */
 	}
 
 	return 0;
@@ -139,6 +149,9 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
 	switch (pclken->bus) {
 	case STM32_CLOCK_BUS_AHB1:
 	case STM32_CLOCK_BUS_AHB2:
+#ifdef CONFIG_SOC_SERIES_STM32L0X
+	case STM32_CLOCK_BUS_IOP:
+#endif /* CONFIG_SOC_SERIES_STM32L0X */
 		*rate = ahb_clock;
 		break;
 	case STM32_CLOCK_BUS_APB1:
diff --git a/drivers/clock_control/stm32l0x_ll_clock.c b/drivers/clock_control/stm32l0x_ll_clock.c
new file mode 100644
index 00000000000..7578c9d5940
--- /dev/null
+++ b/drivers/clock_control/stm32l0x_ll_clock.c
@@ -0,0 +1,43 @@
+/*
+ *
+ * Copyright (c) 2018 Ilya Tagunov
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <soc.h>
+#include <soc_registers.h>
+#include <clock_control.h>
+#include <misc/util.h>
+#include <clock_control/stm32_clock_control.h>
+#include "stm32_ll_clock.h"
+
+
+#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
+
+/* Macros to fill up multiplication and division factors values */
+#define _pll_mul(v) LL_RCC_PLL_MUL_ ## v
+#define pll_mul(v) _pll_mul(v)
+
+#define _pll_div(v) LL_RCC_PLL_DIV_ ## v
+#define pll_div(v) _pll_div(v)
+
+/**
+ * @brief Fill PLL configuration structure
+ */
+void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
+{
+	pllinit->PLLMul = pll_mul(CONFIG_CLOCK_STM32_PLL_MULTIPLIER);
+	pllinit->PLLDiv = pll_div(CONFIG_CLOCK_STM32_PLL_DIVISOR);
+}
+
+#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
+
+/**
+ * @brief Activate default clocks
+ */
+void config_enable_default_clocks(void)
+{
+	/* Nothing for now */
+}
diff --git a/include/dt-bindings/clock/stm32_clock.h b/include/dt-bindings/clock/stm32_clock.h
index 2130b56c5c6..cef35c078f9 100644
--- a/include/dt-bindings/clock/stm32_clock.h
+++ b/include/dt-bindings/clock/stm32_clock.h
@@ -12,6 +12,7 @@
 #define STM32_CLOCK_BUS_APB1    2
 #define STM32_CLOCK_BUS_APB2    3
 #define STM32_CLOCK_BUS_APB1_2  4
+#define STM32_CLOCK_BUS_IOP     5
 
 
 #endif /* __STM32_CLOCK_H */