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x86: declare internal API for interrupt controllers

Browse source 
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.

Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.

Contents of the API:

- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.

- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags

- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced

- In assembly language domain, _irq_controller_eoi implements
EOI handling.

- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.

Specific changes made:

- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.

- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.

- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.

- Unused APIs removed, or folded into calling code when used just once.

- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway

Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2016-08-02 12:05:08 -07:00
commit e98ac235e6
22 changed files with 432 additions and 680 deletions
Download patch file Download diff file Expand all files Collapse all files

8
arch/x86/Kconfig
View file

@ -265,6 +265,14 @@ config IRQ_OFFLOAD_VECTOR
config XIP config XIP
default n default n
config X86_FIXED_IRQ_MAPPING
bool
default n
help
Specify whether the current interrupt controller in use has a fixed
mapping between IDT vectors and IRQ lines.
endmenu endmenu

4
arch/x86/core/fatal.c
View file

@ -27,7 +27,7 @@
#include <nanokernel.h> #include <nanokernel.h>
#include <nano_private.h> #include <nano_private.h>
#include <misc/printk.h> #include <misc/printk.h>
#include <drivers/loapic.h> #include <arch/x86/irq_controller.h>
#include <exception.h> #include <exception.h>
__weak void _debug_fatal_hook(const NANO_ESF *esf) { ARG_UNUSED(esf); } __weak void _debug_fatal_hook(const NANO_ESF *esf) { ARG_UNUSED(esf); }
@ -82,7 +82,7 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
case _NANO_ERR_SPURIOUS_INT: case _NANO_ERR_SPURIOUS_INT:
printk("***** Unhandled interrupt vector %d occurred! " printk("***** Unhandled interrupt vector %d occurred! "
"*****\n", _loapic_isr_vector_get()); "*****\n", _irq_controller_isr_vector_get());
break; break;
case _NANO_ERR_INVALID_TASK_EXIT: case _NANO_ERR_INVALID_TASK_EXIT:

20
arch/x86/core/intstub.S
View file

@ -30,8 +30,7 @@
#include <arch/x86/asm.h> #include <arch/x86/asm.h>
#include <offsets.h> /* nanokernel structure offset definitions */ #include <offsets.h> /* nanokernel structure offset definitions */
#include <arch/cpu.h> /* _NANO_ERR_SPURIOUS_INT */ #include <arch/cpu.h> /* _NANO_ERR_SPURIOUS_INT */
#include <drivers/loapic.h> /* LOAPIC_EOI */ #include <arch/x86/irq_controller.h>
/* exports (internal APIs) */ /* exports (internal APIs) */
@ -288,19 +287,10 @@ SECTION_FUNC(TEXT, _IntExitWithEoi)
*/ */
popl %eax popl %eax
#endif #endif
#if CONFIG_EOI_FORWARDING_BUG
call _lakemont_eoi /* irq_controller.h interface */
#else _irq_controller_eoi
xorl %eax, %eax /* zeroes eax */
/* TODO not great to have hard-coded LOAPIC stuff here. When
* we get around to introducing the interrupt controller abstraction
* layer, the in-use IRQ controller code will define an ASM macro
* with a specific name which does the correct thing for the particular
* controller.
*/
loapic_eoi_reg = (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
movl %eax, loapic_eoi_reg /* tell LOAPIC the IRQ is handled */
#endif
jmp _IntExitWithCli jmp _IntExitWithCli
/** /**

4
arch/x86/include/kernel_event_logger_arch.h
View file

@ -22,7 +22,7 @@
#ifndef __KERNEL_EVENT_LOGGER_ARCH_H__ #ifndef __KERNEL_EVENT_LOGGER_ARCH_H__
#define __KERNEL_EVENT_LOGGER_ARCH_H__ #define __KERNEL_EVENT_LOGGER_ARCH_H__
#include <drivers/loapic.h> #include <arch/x86/irq_controller.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -38,7 +38,7 @@ extern "C" {
*/ */
static inline int _sys_current_irq_key_get(void) static inline int _sys_current_irq_key_get(void)
{ {
return _loapic_isr_vector_get(); return _irq_controller_isr_vector_get();
} }
#ifdef __cplusplus #ifdef __cplusplus

4
arch/x86/soc/quark_d2000/Kbuild
View file

@ -3,4 +3,6 @@ ccflags-y +=-I$(srctree)/include/drivers
ccflags-y +=-I$(srctree)/drivers ccflags-y +=-I$(srctree)/drivers
asflags-y := ${ccflags-y} asflags-y := ${ccflags-y}
obj-$(CONFIG_SOC_QUARK_D2000) = soc.o # Force build system to create built-in.o even though we don't
# have any C files to compile
obj- = dummy.o

32
arch/x86/soc/quark_d2000/soc.c
View file

@ -1,32 +0,0 @@
/*
* Copyright (c) 2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief System/hardware module for the Quark D2000 BSP
*
* This module provides routines to initialize and support board-level
* hardware for the Quark D2000 BSP.
*/
#include <nanokernel.h>
#include "soc.h"
#include <drivers/mvic.h>
#include <init.h>
#ifdef CONFIG_MVIC
SYS_INIT(_mvic_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /* CONFIG_IOAPIC */

12
arch/x86/soc/quark_d2000/soc.h
View file

@ -28,10 +28,6 @@
#include <uart.h> #include <uart.h>
#include <drivers/ioapic.h> #include <drivers/ioapic.h>
#define INT_VEC_IRQ0 0x20 /* Vector number for IRQ0 */
#define FIXED_HARDWARE_IRQ_TO_VEC_MAPPING(x) (INT_VEC_IRQ0 + x)
#define IOAPIC_LO32_RTE_SUPPORTED_MASK (IOAPIC_INT_MASK | IOAPIC_TRIGGER_MASK)
/* Base Register */ /* Base Register */
#define SCSS_REGISTER_BASE 0xB0800000 #define SCSS_REGISTER_BASE 0xB0800000
@ -43,14 +39,6 @@
#define INT_UNMASK_IA (~0x00000001) #define INT_UNMASK_IA (~0x00000001)
/*
* Local APIC (LOAPIC) device information (Intel loapic)
*/
#define LOAPIC_IRQ_BASE CONFIG_LOAPIC_TIMER_IRQ
#define LOAPIC_IRQ_COUNT 1
#define LOAPIC_LVT_REG_SPACING 0x10
/* /*
* PINMUX configuration settings * PINMUX configuration settings
*/ */

7
arch/x86/soc/quark_se/eoi.c
View file

@ -25,8 +25,7 @@
*/ */
#include <nanokernel.h> #include <nanokernel.h>
#include <drivers/loapic.h> #include <arch/x86/irq_controller.h>
#include <drivers/ioapic.h>
#include <sys_io.h> #include <sys_io.h>
#include <interrupt_controller/ioapic_priv.h> #include <interrupt_controller/ioapic_priv.h>
@ -37,8 +36,8 @@ void _lakemont_eoi(void)
* we have is the vector # in the IDT. So unconditionally * we have is the vector # in the IDT. So unconditionally
* write to IOAPIC_EOI for every interrupt * write to IOAPIC_EOI for every interrupt
*/ */
sys_write32(_loapic_isr_vector_get(), CONFIG_IOAPIC_BASE_ADDRESS + sys_write32(_irq_controller_isr_vector_get(),
IOAPIC_EOI); CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_EOI);
/* Send EOI to the LOAPIC as well */ /* Send EOI to the LOAPIC as well */
sys_write32(0, CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI); sys_write32(0, CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI);

1
boards/quark_d2000_crb/quark_d2000_crb_defconfig
View file

@ -3,7 +3,6 @@ CONFIG_SOC_QUARK_D2000=y
CONFIG_BOARD_QUARK_D2000_CRB=y CONFIG_BOARD_QUARK_D2000_CRB=y
CONFIG_CPU_MINUTEIA=y CONFIG_CPU_MINUTEIA=y
CONFIG_IDT_NUM_VECTORS=64 CONFIG_IDT_NUM_VECTORS=64
CONFIG_LOAPIC_TIMER_DIVIDER_UNSUPPORTED=y
CONFIG_UART_QMSI=y CONFIG_UART_QMSI=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y CONFIG_CONSOLE=y

15
drivers/interrupt_controller/Kconfig
View file

@ -30,7 +30,7 @@ config LOAPIC
config LOAPIC_BASE_ADDRESS config LOAPIC_BASE_ADDRESS
hex "Local APIC Base Address" hex "Local APIC Base Address"
default 0xFEE00000 default 0xFEE00000
depends on LOAPIC || MVIC depends on LOAPIC
help help
This option specifies the base address of the Local APIC device. This option specifies the base address of the Local APIC device.
@ -76,7 +76,7 @@ config IOAPIC_DEBUG
config IOAPIC_BASE_ADDRESS config IOAPIC_BASE_ADDRESS
hex "IO-APIC Base Address" hex "IO-APIC Base Address"
default 0xFEC00000 default 0xFEC00000
depends on IOAPIC || MVIC depends on IOAPIC
help help
This option specifies the base address of the IO-APIC device. This option specifies the base address of the IO-APIC device.
@ -95,6 +95,7 @@ config MVIC
bool "Intel Quark D2000 Interrupt Controller (MVIC)" bool "Intel Quark D2000 Interrupt Controller (MVIC)"
default n default n
depends on X86 depends on X86
select X86_FIXED_IRQ_MAPPING
help help
The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is
configured by default to support 32 external interrupt lines. Unlike the configured by default to support 32 external interrupt lines. Unlike the
@ -102,6 +103,16 @@ config MVIC
not programmable. In addition, the priorities of these interrupt not programmable. In addition, the priorities of these interrupt
lines are also fixed. lines are also fixed.
config MVIC_TIMER_IRQ
int "IRQ line to use for timer interrupt"
range 0 15
default 0
depends on MVIC
help
Specify the IRQ line to use for the timer interrupt. This should be
an IRQ line unused by any hardware. If nested interrupts are enabled,
higher interrupt lines have priority.
config ARCV2_INTERRUPT_UNIT config ARCV2_INTERRUPT_UNIT
bool "ARCv2 Interrupt Unit" bool "ARCv2 Interrupt Unit"
default y default y

3
drivers/interrupt_controller/Makefile
View file

@ -1,8 +1,7 @@
obj-${CONFIG_PIC_DISABLE} = i8259.o obj-${CONFIG_PIC_DISABLE} = i8259.o
obj-$(CONFIG_LOAPIC)$(CONFIG_MVIC) += system_apic.o
obj-$(CONFIG_MVIC) += mvic.o obj-$(CONFIG_MVIC) += mvic.o
obj-$(CONFIG_LOAPIC) += loapic_intr.o obj-$(CONFIG_LOAPIC) += loapic_intr.o system_apic.o
obj-$(CONFIG_IOAPIC) += ioapic_intr.o obj-$(CONFIG_IOAPIC) += ioapic_intr.o
obj-$(CONFIG_LOAPIC_SPURIOUS_VECTOR) += loapic_spurious.o obj-$(CONFIG_LOAPIC_SPURIOUS_VECTOR) += loapic_spurious.o

65
drivers/interrupt_controller/loapic_intr.c
View file

@ -208,14 +208,14 @@ uint32_t loapic_suspend_buf[LOPIC_SUSPEND_BITS_REQD / 32] = {0};
* *
*/ */
int _loapic_init(struct device *unused) static int _loapic_init(struct device *unused)
{ {
ARG_UNUSED(unused); ARG_UNUSED(unused);
int32_t loApicMaxLvt; /* local APIC Max LVT */ int32_t loApicMaxLvt; /* local APIC Max LVT */
/* enable the Local APIC */ /* enable the Local APIC */
sys_write32(sys_read32(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR)
_loapic_enable(); | LOAPIC_ENABLE, CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR);
loApicMaxLvt = (*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_VER) & loApicMaxLvt = (*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_VER) &
LOAPIC_MAXLVT_MASK) >> 16; LOAPIC_MAXLVT_MASK) >> 16;
@ -262,60 +262,29 @@ int _loapic_init(struct device *unused)
#if CONFIG_LOAPIC_SPURIOUS_VECTOR #if CONFIG_LOAPIC_SPURIOUS_VECTOR
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) = *(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) =
(*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) & 0xFFFFFF00) (*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR)
& 0xFFFFFF00)
| (LOAPIC_SPURIOUS_VECTOR_ID & 0xFF); | (LOAPIC_SPURIOUS_VECTOR_ID & 0xFF);
#endif #endif
/* discard a pending interrupt if any */ /* discard a pending interrupt if any */
_loapic_eoi(); #if CONFIG_EOI_FORWARDING_BUG
_lakemont_eoi();
#else
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
#endif
return 0; return 0;
} }
/**
*
* @brief Enable the Local xAPIC
*
* This routine enables the Local xAPIC.
*
* @return N/A
*/
void _loapic_enable(void)
{
int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) |= LOAPIC_ENABLE;
irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
}
/**
*
* @brief Disable the Local xAPIC
*
* This routine disables the Local xAPIC.
*
* @return N/A
*/
void _loapic_disable(void)
{
int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) &=
~LOAPIC_ENABLE;
irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
}
/** /**
* *
* @brief Set the vector field in the specified RTE * @brief Set the vector field in the specified RTE
* *
* This routine is utilized by the interrupt controller's _SysIntVecAlloc() * This routine is utilized by the interrupt controller's
* routine (which exists to support the irq_connect_dynamic() API). Once * _interrupt_vector_allocate() routine (which exists to support the
* a vector has been allocated, this routine is invoked to update the LVT * irq_connect_dynamic() API). Once a vector has been allocated, this routine
* entry associated with <irq> with the vector. * is invoked to update the LVT entry associated with <irq> with the vector.
* *
* @return N/A * @return N/A
*/ */
@ -439,7 +408,7 @@ void _loapic_irq_disable(unsigned int irq)
* *
* @return The vector of the interrupt that is currently being processed. * @return The vector of the interrupt that is currently being processed.
*/ */
int _loapic_isr_vector_get(void) int __irq_controller_isr_vector_get(void)
{ {
int pReg, block; int pReg, block;
@ -490,7 +459,7 @@ static int loapic_suspend(struct device *port, int pm_policy)
return 0; return 0;
} }
int loapic_resume(struct device *port, int pm_policy) static int loapic_resume(struct device *port, int pm_policy)
{ {
int loapic_irq; int loapic_irq;

519
drivers/interrupt_controller/mvic.c
View file

@ -45,398 +45,24 @@
#include <nanokernel.h> #include <nanokernel.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <misc/__assert.h> #include <misc/__assert.h>
#include <misc/util.h>
#include <init.h>
#include <arch/x86/irq_controller.h>
#include "board.h"
#include <toolchain.h> static inline uint32_t compute_ioregsel(unsigned int irq)
#include <sections.h>
#include <drivers/ioapic.h> /* IO APIC public API declarations. */
#include <drivers/loapic.h> /* Local APIC public API declarations.*/
/* defines */
/* IO APIC direct register offsets */
#define IOAPIC_IND 0x00 /* Index Register - MVIC IOREGSEL register */
#define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
/* MVIC IOREGSEL register usage defines */
#define MVIC_LOW_NIBBLE_MASK 0x07
#define MVIC_HIGH_NIBBLE_MASK 0x18
/* MVIC Local APIC Vector Table Bits */
#define LOAPIC_VECTOR 0x000000ff /* vectorNo */
/* MVIC Local APIC Spurious-Interrupt Register Bits */
#define LOAPIC_ENABLE 0x100 /* APIC Enabled */
#define LOAPIC_MVIC_ISR 0x110 /* MVIC In-Service Register offset */
/* forward declarations */
static void _mvic_rte_set(unsigned int irq, uint32_t value);
static uint32_t _mvic_rte_get(unsigned int irq);
static void _mvic_rte_update(unsigned int irq, uint32_t value,
uint32_t mask);
/*
* The functions irq_enable() and irq_disable() are implemented
* in the platforms that incorporate this interrupt controller driver due to the
* IRQ virtualization imposed by the platform.
*/
/**
*
* @brief initialize the MVIC IO APIC and local APIC register sets.
*
* This routine initializes the Quark D2000 Interrupt Controller (MVIC).
* This routine replaces the standard Local APIC / IO APIC init routines.
*
* @returns: N/A
*/
int _mvic_init(struct device *unused)
{ {
ARG_UNUSED(unused);
int32_t ix; /* Interrupt line register index */
uint32_t rteValue; /* value to copy into interrupt line register */
/*
* The platform must define the CONFIG_IOAPIC_NUM_RTES macro to indicate the number
* of redirection table entries supported by the IOAPIC on the board.
*
* By default mask all interrupt lines and set default sensitivity to edge.
*
*/
rteValue = IOAPIC_EDGE | IOAPIC_INT_MASK;
for (ix = 0; ix < CONFIG_IOAPIC_NUM_RTES; ix++) {
_mvic_rte_set(ix, rteValue);
}
/* enable the MVIC Local APIC */
_loapic_enable();
/* reset the TPR, and TIMER_ICR */
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TPR) = (int)0x0;
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_ICR) = (int)0x0;
/* program Local Vector Table for the Virtual Wire Mode */
/* lock the MVIC timer interrupt, set which IRQ line should be
* used for timer interrupts (this is unlike LOAPIC where the
* vector is programmed instead).
*/
__ASSERT_NO_MSG(CONFIG_LOAPIC_TIMER_IRQ <= 15);
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER) =
LOAPIC_LVT_MASKED | CONFIG_LOAPIC_TIMER_IRQ;
/* discard a pending interrupt if any */
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
return 0;
}
/**
*
* @brief Send EOI (End Of Interrupt) signal to IO APIC
*
* This routine sends an EOI signal to the IO APIC's interrupting source.
*
* All line interrupts on Quark D2000 are EOI'ed with local APIC EOI register.
*
* @param irq INT number to send EOI
*
* @returns: N/A
*/
void _ioapic_eoi(unsigned int irq)
{
_loapic_eoi();
}
/**
*
* @brief Get EOI (End Of Interrupt) information
*
* This routine returns EOI signalling information for a specific IRQ.
*
* @param irq INTIN number of interest
* @param argRequired ptr to "argument required" result area
* @param arg ptr to "argument value" result area
*
* @returns: address of routine to be called to signal EOI;
* as a side effect, also passes back indication if routine requires
* an interrupt vector argument and what the argument value should be
*/
void *_ioapic_eoi_get(unsigned int irq, char *argRequired, void **arg)
{
/* indicate that an argument to the EOI handler is required */
*argRequired = 1;
/*
* The parameter to the ioApicIntEoi() routine is the vector programmed
* into the redirection table. The platform _SysIntVecAlloc() routine
* must invoke _IoApicIntEoiGet() after _IoApicRedVecSet() to ensure the
* redirection table contains the desired interrupt vector.
*
* Vectors fixed on this CPU Arch, no memory location on this CPU
* arch with this information.
*/
*arg = NULL;
/* lo eoi always used on this CPU arch. */
return _loapic_eoi;
}
/**
*
* @brief Enable a specified APIC interrupt input line
*
* This routine enables a specified APIC interrupt input line.
*
* @param irq INTIN number to enable
*
* @returns: N/A
*/
void _ioapic_irq_enable(unsigned int irq)
{
_mvic_rte_update(irq, 0, IOAPIC_INT_MASK);
}
/**
*
* @brief disable a specified APIC interrupt input line
*
* This routine disables a specified APIC interrupt input line.
*
* @param irq INTIN number to disable
*
* @returns: N/A
*/
void _ioapic_irq_disable(unsigned int irq)
{
_mvic_rte_update(irq, IOAPIC_INT_MASK, IOAPIC_INT_MASK);
}
/**
*
* @brief Programs Rte interrupt line register.
*
* Always mask interrupt as part of programming like standard IOAPIC
* version of this routine.
* Vector is fixed by this HW and is unused.
* Or in flags for trigger bit.
*
* @param irq Virtualized IRQ
* @param vector Vector Number
* @param flags Interrupt flags
*
* @returns: N/A
*/
void _ioapic_irq_set(unsigned int irq, unsigned int vector, uint32_t flags)
{
uint32_t rteValue; /* value to copy into Rte register */
ARG_UNUSED(vector);
rteValue = IOAPIC_INT_MASK | flags;
_mvic_rte_set(irq, rteValue);
}
/**
*
* @brief program interrupt vector for specified irq
*
* Fixed vector on this HW. Nothing to do.
*
* @param irq Interrupt number
* @param vector Vector number
*
* @returns: N/A
*/
void _ioapic_int_vec_set(unsigned int irq, unsigned int vector)
{
ARG_UNUSED(irq);
ARG_UNUSED(vector);
}
/**
*
* @brief Enable the MVIC Local APIC
*
* This routine enables the MVIC Local APIC.
*
* @returns: N/A
*/
void _loapic_enable(void)
{
int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) |= LOAPIC_ENABLE;
irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
}
/**
*
* @brief Disable the MVIC Local APIC.
*
* This routine disables the MVIC Local APIC.
*
* @returns: N/A
*/
void _loapic_disable(void)
{
int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) &= ~LOAPIC_ENABLE;
irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
}
/**
*
* @brief Set the vector field in the specified RTE
*
* Fixed vectors on this HW. Nothing to do.
*
* @param irq IRQ number of the interrupt
* @param vector vector to copy into the LVT
*
* @returns N/A
*/
void _loapic_int_vec_set(unsigned int irq, unsigned int vector)
{
ARG_UNUSED(irq);
ARG_UNUSED(vector);
}
/**
*
* @brief enable an individual LOAPIC interrupt (IRQ)
*
* This routine clears the interrupt mask bit in the LVT for the specified IRQ
*
* @param irq IRQ number of the interrupt
*
* @returns N/A
*/
void _loapic_irq_enable(unsigned int irq)
{
volatile int *pLvt; /* pointer to local vector table */
int32_t oldLevel; /* previous interrupt lock level */
/*
* irq is actually an index to local APIC LVT register.
* ASSERT if out of range for MVIC implementation.
*/
__ASSERT_NO_MSG(irq < LOAPIC_IRQ_COUNT);
/*
* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
* and ths assumption concerning LVT spacing.
*/
pLvt = (volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER +
(irq * LOAPIC_LVT_REG_SPACING));
/* clear the mask bit in the LVT */
oldLevel = irq_lock();
*pLvt = *pLvt & ~LOAPIC_LVT_MASKED;
irq_unlock(oldLevel);
}
/**
*
* @brief disable an individual LOAPIC interrupt (IRQ)
*
* This routine clears the interrupt mask bit in the LVT for the specified IRQ
*
* @param irq IRQ number of the interrupt
*
* @returns N/A
*/
void _loapic_irq_disable(unsigned int irq)
{
volatile int *pLvt; /* pointer to local vector table */
int32_t oldLevel; /* previous interrupt lock level */
/*
* irq is actually an index to local APIC LVT register.
* ASSERT if out of range for MVIC implementation.
*/
__ASSERT_NO_MSG(irq < LOAPIC_IRQ_COUNT);
/*
* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
* and ths assumption concerning LVT spacing.
*/
pLvt = (volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER +
(irq * LOAPIC_LVT_REG_SPACING));
/* set the mask bit in the LVT */
oldLevel = irq_lock();
*pLvt = *pLvt | LOAPIC_LVT_MASKED;
irq_unlock(oldLevel);
}
/**
*
* @brief read a 32 bit MVIC IO APIC register
*
* @param irq INTIN number
*
* @returns register value
*/
static uint32_t _mvic_rte_get(unsigned int irq)
{
uint32_t value; /* value */
int key; /* interrupt lock level */
volatile unsigned int *rte;
volatile unsigned int *index;
unsigned int low_nibble; unsigned int low_nibble;
unsigned int high_nibble; unsigned int high_nibble;
index = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND); __ASSERT(irq < MVIC_NUM_RTES, "invalid irq line %d", irq);
rte = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA);
/* Set index in the IOREGSEL */
__ASSERT(irq < CONFIG_IOAPIC_NUM_RTES, "INVL");
low_nibble = ((irq & MVIC_LOW_NIBBLE_MASK) << 0x1); low_nibble = ((irq & MVIC_LOW_NIBBLE_MASK) << 0x1);
high_nibble = ((irq & MVIC_HIGH_NIBBLE_MASK) << 0x2); high_nibble = ((irq & MVIC_HIGH_NIBBLE_MASK) << 0x2);
return low_nibble | high_nibble;
/* lock interrupts to ensure indirect addressing works "atomically" */
key = irq_lock();
*(index) = high_nibble | low_nibble;
value = *(rte);
irq_unlock(key);
return value;
} }
/** /**
* *
* @brief write to 32 bit MVIC IO APIC register * @brief write to 32 bit MVIC IO APIC register
@ -449,30 +75,23 @@ static uint32_t _mvic_rte_get(unsigned int irq)
static void _mvic_rte_set(unsigned int irq, uint32_t value) static void _mvic_rte_set(unsigned int irq, uint32_t value)
{ {
int key; /* interrupt lock level */ int key; /* interrupt lock level */
volatile unsigned int *rte; uint32_t regsel;
volatile unsigned int *index;
unsigned int low_nibble;
unsigned int high_nibble;
index = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND); __ASSERT(!(value & ~MVIC_IOWIN_SUPPORTED_BITS_MASK),
rte = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA); "invalid IRQ flags %x for irq %d", value, irq);
/* Set index in the IOREGSEL */ regsel = compute_ioregsel(irq);
__ASSERT(irq < CONFIG_IOAPIC_NUM_RTES, "INVL");
low_nibble = ((irq & MVIC_LOW_NIBBLE_MASK) << 0x1);
high_nibble = ((irq & MVIC_HIGH_NIBBLE_MASK) << 0x2);
/* lock interrupts to ensure indirect addressing works "atomically" */ /* lock interrupts to ensure indirect addressing works "atomically" */
key = irq_lock(); key = irq_lock();
*(index) = high_nibble | low_nibble; sys_write32(regsel, MVIC_IOREGSEL);
*(rte) = (value & IOAPIC_LO32_RTE_SUPPORTED_MASK); sys_write32(value, MVIC_IOWIN);
irq_unlock(key); irq_unlock(key);
} }
/** /**
* *
* @brief modify interrupt line register. * @brief modify interrupt line register.
@ -485,9 +104,106 @@ static void _mvic_rte_set(unsigned int irq, uint32_t value)
*/ */
static void _mvic_rte_update(unsigned int irq, uint32_t value, uint32_t mask) static void _mvic_rte_update(unsigned int irq, uint32_t value, uint32_t mask)
{ {
_mvic_rte_set(irq, (_mvic_rte_get(irq) & ~mask) | (value & mask)); int key;
uint32_t regsel, old_value, updated_value;
__ASSERT(!(value & ~MVIC_IOWIN_SUPPORTED_BITS_MASK),
"invalid IRQ flags %x for irq %d", value, irq);
regsel = compute_ioregsel(irq);
key = irq_lock();
sys_write32(regsel, MVIC_IOREGSEL);
old_value = sys_read32(MVIC_IOWIN);
updated_value = (old_value & ~mask) | (value & mask);
sys_write32(updated_value, MVIC_IOWIN);
irq_unlock(key);
} }
/**
*
* @brief initialize the MVIC IO APIC and local APIC register sets.
*
* This routine initializes the Quark D2000 Interrupt Controller (MVIC).
* This routine replaces the standard Local APIC / IO APIC init routines.
*
* @returns: N/A
*/
static int _mvic_init(struct device *unused)
{
ARG_UNUSED(unused);
int i;
/* By default mask all interrupt lines */
for (i = 0; i < MVIC_NUM_RTES; i++) {
_mvic_rte_set(i, MVIC_IOWIN_MASK);
}
/* reset the task priority and timer initial count registers */
sys_write32(0, MVIC_TPR);
sys_write32(0, MVIC_ICR);
/* Initialize and mask the timer interrupt.
* Bits 0-3 program the interrupt line number we will use
* for the timer interrupt.
*/
__ASSERT(CONFIG_MVIC_TIMER_IRQ < 16,
"Bad irq line %d chosen for timer irq", CONFIG_MVIC_TIMER_IRQ);
sys_write32(MVIC_LVTTIMER_MASK | CONFIG_MVIC_TIMER_IRQ, MVIC_LVTTIMER);
/* discard a pending interrupt if any */
sys_write32(0, MVIC_EOI);
return 0;
}
SYS_INIT(_mvic_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
void _arch_irq_enable(unsigned int irq)
{
if (irq == CONFIG_MVIC_TIMER_IRQ) {
sys_write32(sys_read32(MVIC_LVTTIMER) & ~MVIC_LVTTIMER_MASK,
MVIC_LVTTIMER);
} else {
_mvic_rte_update(irq, 0, MVIC_IOWIN_MASK);
}
}
void _arch_irq_disable(unsigned int irq)
{
if (irq == CONFIG_MVIC_TIMER_IRQ) {
sys_write32(sys_read32(MVIC_LVTTIMER) | MVIC_LVTTIMER_MASK,
MVIC_LVTTIMER);
} else {
_mvic_rte_update(irq, MVIC_IOWIN_MASK, MVIC_IOWIN_MASK);
}
}
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
uint32_t flags)
{
ARG_UNUSED(vector);
/* Vector argument always ignored. There are no triggering options
* for the timer, so nothing to do at all for that case. Other I/O
* interrupts need their triggering set
*/
if (irq != CONFIG_MVIC_TIMER_IRQ) {
_mvic_rte_set(irq, MVIC_IOWIN_MASK | flags);
} else {
__ASSERT(flags == 0,
"Timer interrupt cannot have triggering flags set");
}
}
/** /**
* @brief Find the currently executing interrupt vector, if any * @brief Find the currently executing interrupt vector, if any
* *
@ -505,12 +221,11 @@ static void _mvic_rte_update(unsigned int irq, uint32_t value, uint32_t mask)
* *
* @return The vector of the interrupt that is currently being processed. * @return The vector of the interrupt that is currently being processed.
*/ */
int _loapic_isr_vector_get(void) int __irq_controller_isr_vector_get(void)
{ {
/* pointer to ISR vector table */ /* In-service register value */
volatile int *pReg; int isr;
pReg = (volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_MVIC_ISR); isr = sys_read32(MVIC_ISR);
return 32 + (find_msb_set(isr) - 1);
return 32 + (find_msb_set(*pReg) - 1);
} }

11
drivers/interrupt_controller/system_apic.c
View file

@ -29,6 +29,8 @@
#include <drivers/sysapic.h> #include <drivers/sysapic.h>
#include <irq.h> #include <irq.h>
#define IS_IOAPIC_IRQ(irq) (irq < LOAPIC_IRQ_BASE)
#define HARDWARE_IRQ_LIMIT ((LOAPIC_IRQ_BASE + LOAPIC_IRQ_COUNT) - 1)
/** /**
* *
@ -52,8 +54,11 @@
* @param flags interrupt flags * @param flags interrupt flags
* *
*/ */
void _SysIntVecProgram(unsigned int vector, unsigned int irq, uint32_t flags) void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
uint32_t flags)
{ {
__ASSERT(irq >= 0 && irq <= HARDWARE_IRQ_LIMIT, "invalid irq line");
if (IS_IOAPIC_IRQ(irq)) { if (IS_IOAPIC_IRQ(irq)) {
_ioapic_irq_set(irq, vector, flags); _ioapic_irq_set(irq, vector, flags);
} else { } else {
@ -73,7 +78,7 @@ void _SysIntVecProgram(unsigned int vector, unsigned int irq, uint32_t flags)
* *
* The irq_enable() routine is provided by the interrupt controller driver due * The irq_enable() routine is provided by the interrupt controller driver due
* to the IRQ virtualization that is performed by this platform. See the * to the IRQ virtualization that is performed by this platform. See the
* comments in _SysIntVecAlloc() for more information regarding IRQ * comments in _interrupt_vector_allocate() for more information regarding IRQ
* virtualization. * virtualization.
* *
* @return N/A * @return N/A
@ -93,7 +98,7 @@ void _arch_irq_enable(unsigned int irq)
* *
* The irq_disable() routine is provided by the interrupt controller driver due * The irq_disable() routine is provided by the interrupt controller driver due
* to the IRQ virtualization that is performed by this platform. See the * to the IRQ virtualization that is performed by this platform. See the
* comments in _SysIntVecAlloc() for more information regarding IRQ * comments in _interrupt_vector_allocate() for more information regarding IRQ
* virtualization. * virtualization.
* *
* @return N/A * @return N/A

10
drivers/timer/Kconfig
View file

@ -115,16 +115,6 @@ config LOAPIC_TIMER_IRQ_PRIORITY
help help
This options specifies the IRQ priority used by the LOAPIC timer. This options specifies the IRQ priority used by the LOAPIC timer.
config LOAPIC_TIMER_DIVIDER_UNSUPPORTED
bool "LOAPIC timer divider unsupported"
depends on LOAPIC_TIMER && MVIC && X86
default n
help
This option selects if Local Apic Timer divider register is supported.
The MVIC interrupt controller does not provide the Timer Divide
Configuration Register (TDC).
config ARCV2_TIMER config ARCV2_TIMER
bool "ARC Timer" bool "ARC Timer"
default y default y

85
drivers/timer/loapic_timer.c
View file

@ -80,7 +80,7 @@
#include <sections.h> #include <sections.h>
#include <sys_clock.h> #include <sys_clock.h>
#include <drivers/system_timer.h> #include <drivers/system_timer.h>
#include <drivers/loapic.h> /* LOAPIC registers */ #include <arch/x86/irq_controller.h>
#include <power.h> #include <power.h>
#include <device.h> #include <device.h>
@ -104,15 +104,31 @@
#define LOAPIC_TIMER_PERIODIC 0x00020000 /* Timer Mode: Periodic */ #define LOAPIC_TIMER_PERIODIC 0x00020000 /* Timer Mode: Periodic */
/* Helpful macros and inlines for programming timer */ /* Helpful macros and inlines for programming timer.
* We support both standard LOAPIC, and MVIC which has a similar
* interface
*/
#if defined(CONFIG_LOAPIC)
#define _REG_TIMER ((volatile uint32_t *) \ #define _REG_TIMER ((volatile uint32_t *) \
(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER)) (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER))
#define _REG_TIMER_ICR ((volatile uint32_t *) \ #define _REG_TIMER_ICR ((volatile uint32_t *) \
(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_ICR)) (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_ICR))
#define _REG_TIMER_CCR ((volatile uint32_t *) \ #define _REG_TIMER_CCR ((volatile uint32_t *) \
(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_CCR)) (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_CCR))
#define _REG_TIMER_CFG ((volatile uint32_t *) \ #define _REG_TIMER_CFG ((volatile uint32_t *) \
(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_CONFIG)) (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_CONFIG))
#define TIMER_IRQ CONFIG_LOAPIC_TIMER_IRQ
#define TIMER_IRQ_PRIORITY CONFIG_LOAPIC_TIMER_IRQ_PRIORITY
#elif defined(CONFIG_MVIC)
#define _REG_TIMER ((volatile uint32_t *)MVIC_LVTTIMER)
#define _REG_TIMER_ICR ((volatile uint32_t *)MVIC_ICR)
#define _REG_TIMER_CCR ((volatile uint32_t *)MVIC_CCR)
/* MVIC has no TIMER_CFG register */
#define TIMER_IRQ CONFIG_MVIC_TIMER_IRQ
#define TIMER_IRQ_PRIORITY -1
#endif
#if defined(CONFIG_TICKLESS_IDLE) #if defined(CONFIG_TICKLESS_IDLE)
#define TIMER_MODE_ONE_SHOT 0 #define TIMER_MODE_ONE_SHOT 0
@ -158,38 +174,6 @@ static inline void periodic_mode_set(void)
*_REG_TIMER |= LOAPIC_TIMER_PERIODIC; *_REG_TIMER |= LOAPIC_TIMER_PERIODIC;
} }
#if defined(CONFIG_TICKLESS_IDLE) || \
defined(LOAPIC_TIMER_PERIODIC_WORKAROUND) || \
defined(CONFIG_SYSTEM_CLOCK_DISABLE)
/**
*
* @brief Mask the timer interrupt
*
* This routine disables the LOAPIC timer by masking it.
*
* @return N/A
*/
static inline void timer_interrupt_mask(void)
{
*_REG_TIMER |= LOAPIC_LVT_MASKED;
}
#endif
#if defined(CONFIG_TICKLESS_IDLE) || \
defined(LOAPIC_TIMER_PERIODIC_WORKAROUND)
/**
*
* @brief Unmask the timer interrupt
*
* This routine enables the LOAPIC timer by unmasking it.
*
* @return N/A
*/
static inline void timer_interrupt_unmask(void)
{
*_REG_TIMER &= ~LOAPIC_LVT_MASKED;
}
#endif
/** /**
* *
@ -198,11 +182,10 @@ static inline void timer_interrupt_unmask(void)
* This routine sets value from which the timer will count down. * This routine sets value from which the timer will count down.
* Note that setting the value to zero stops the timer. * Note that setting the value to zero stops the timer.
* *
* @param count Count from which timer is to count down
* @return N/A * @return N/A
*/ */
static inline void initial_count_register_set( static inline void initial_count_register_set(uint32_t count)
uint32_t count /* count from which timer is to count down */
)
{ {
*_REG_TIMER_ICR = count; *_REG_TIMER_ICR = count;
} }
@ -228,14 +211,11 @@ static inline void one_shot_mode_set(void)
* *
* This routine sets rate at which the timer is decremented to match the * This routine sets rate at which the timer is decremented to match the
* external bus frequency. * external bus frequency.
* This is not supported with MVIC, only real LOAPIC.
* *
* @return N/A * @return N/A
*/ */
#if defined(CONFIG_LOAPIC_TIMER_DIVIDER_UNSUPPORTED) #ifndef CONFIG_MVIC
static inline void divide_configuration_register_set(void)
{
}
#else
static inline void divide_configuration_register_set(void) static inline void divide_configuration_register_set(void)
{ {
*_REG_TIMER_CFG = (*_REG_TIMER_CFG & ~0xf) | LOAPIC_TIMER_DIVBY_1; *_REG_TIMER_CFG = (*_REG_TIMER_CFG & ~0xf) | LOAPIC_TIMER_DIVBY_1;
@ -558,17 +538,18 @@ int _sys_clock_driver_init(struct device *device)
tickless_idle_init(); tickless_idle_init();
#ifndef CONFIG_MVIC
divide_configuration_register_set(); divide_configuration_register_set();
#endif
initial_count_register_set(cycles_per_tick - 1); initial_count_register_set(cycles_per_tick - 1);
periodic_mode_set(); periodic_mode_set();
IRQ_CONNECT(CONFIG_LOAPIC_TIMER_IRQ, CONFIG_LOAPIC_TIMER_IRQ_PRIORITY, IRQ_CONNECT(TIMER_IRQ, TIMER_IRQ_PRIORITY, _timer_int_handler, 0, 0);
_timer_int_handler, 0, 0);
/* Everything has been configured. It is now safe to enable the /* Everything has been configured. It is now safe to enable the
* interrupt * interrupt
*/ */
irq_enable(CONFIG_LOAPIC_TIMER_IRQ); irq_enable(TIMER_IRQ);
return 0; return 0;
} }
@ -680,14 +661,10 @@ void sys_clock_disable(void)
key = irq_lock(); key = irq_lock();
timer_interrupt_mask(); irq_disable(TIMER_IRQ);
initial_count_register_set(0); initial_count_register_set(0);
irq_unlock(key); irq_unlock(key);
/* disable interrupt in the interrupt controller */
irq_disable(CONFIG_LOAPIC_TIMER_IRQ);
} }
#endif /* CONFIG_SYSTEM_CLOCK_DISABLE */ #endif /* CONFIG_SYSTEM_CLOCK_DISABLE */

51
include/arch/x86/arch.h
View file

@ -25,6 +25,7 @@
#define _ARCH_IFACE_H #define _ARCH_IFACE_H
#include <irq.h> #include <irq.h>
#include <arch/x86/irq_controller.h>
#ifndef _ASMLANGUAGE #ifndef _ASMLANGUAGE
#include <arch/x86/asm_inline.h> #include <arch/x86/asm_inline.h>
@ -76,11 +77,16 @@ extern "C" {
typedef struct s_isrList { typedef struct s_isrList {
/** Address of ISR/stub */ /** Address of ISR/stub */
void *fnc; void *fnc;
/** IRQ associated with the ISR/stub */ /** IRQ associated with the ISR/stub, or -1 if this is not
* associated with a real interrupt; in this case vec must
* not be -1
*/
unsigned int irq; unsigned int irq;
/** Priority associated with the IRQ */ /** Priority associated with the IRQ. Ignored if vec is not -1 */
unsigned int priority; unsigned int priority;
/** Vector number associated with ISR/stub */ /** Vector number associated with ISR/stub, or -1 to assign based
* on priority
*/
unsigned int vec; unsigned int vec;
/** Privilege level associated with ISR/stub */ /** Privilege level associated with ISR/stub */
unsigned int dpl; unsigned int dpl;
@ -148,13 +154,11 @@ typedef struct s_isrList {
* *
* These macros are only intended to be used by IRQ_CONNECT() macro. * These macros are only intended to be used by IRQ_CONNECT() macro.
*/ */
#if CONFIG_MVIC #if CONFIG_X86_FIXED_IRQ_MAPPING
#define _PRIORITY_ARG(irq_p, priority_p) (-1) #define _VECTOR_ARG(irq_p) _IRQ_CONTROLLER_VECTOR_MAPPING(irq_p)
#define _VECTOR_ARG(irq_p) (irq_p + 0x20)
#else #else
#define _PRIORITY_ARG(irq_p, priority_p) (priority_p) #define _VECTOR_ARG(irq_p) (-1)
#define _VECTOR_ARG(irq_p) (-1) #endif /* CONFIG_X86_FIXED_IRQ_MAPPING */
#endif /* CONFIG_MVIC */
/** /**
* Configure a static interrupt. * Configure a static interrupt.
@ -179,14 +183,14 @@ typedef struct s_isrList {
* argument to the ISR, and then the ISR is called. _IntExitWithEoi * argument to the ISR, and then the ISR is called. _IntExitWithEoi
* restores calling context and 'iret's. * restores calling context and 'iret's.
* *
* 4. _SysIntVecProgram() is called at runtime to set the mapping between * 4. _irq_controller_irq_config() is called at runtime to set the mapping
* the vector and the IRQ line. * between the vector and the IRQ line as well as triggering flags
* *
* @param irq_p IRQ line number * @param irq_p IRQ line number
* @param priority_p Interrupt priority * @param priority_p Interrupt priority
* @param isr_p Interrupt service routine * @param isr_p Interrupt service routine
* @param isr_param_p ISR parameter * @param isr_param_p ISR parameter
* @param flags_p IRQ triggering options * @param flags_p IRQ triggering options, as defined in irq_controller.h
* *
* @return The vector assigned to this interrupt * @return The vector assigned to this interrupt
*/ */
@ -211,18 +215,19 @@ typedef struct s_isrList {
: \ : \
: [isr] "i" (isr_p), \ : [isr] "i" (isr_p), \
[isr_param] "i" (isr_param_p), \ [isr_param] "i" (isr_param_p), \
[priority] "i" _PRIORITY_ARG(irq_p, priority_p), \ [priority] "i" (priority_p), \
[vector] "i" _VECTOR_ARG(irq_p), \ [vector] "i" _VECTOR_ARG(irq_p), \
[irq] "i" (irq_p)); \ [irq] "i" (irq_p)); \
_SysIntVecProgram(_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), (flags_p)); \ _irq_controller_irq_config(_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), \
(flags_p)); \
_IRQ_TO_INTERRUPT_VECTOR(irq_p); \ _IRQ_TO_INTERRUPT_VECTOR(irq_p); \
}) })
#ifdef CONFIG_MVIC #ifdef CONFIG_X86_FIXED_IRQ_MAPPING
/* Fixed vector-to-irq association mapping. /* Fixed vector-to-irq association mapping.
* No need for the table at all. * No need for the table at all.
*/ */
#define _IRQ_TO_INTERRUPT_VECTOR(irq) (irq + 0x20) #define _IRQ_TO_INTERRUPT_VECTOR(irq) _IRQ_CONTROLLER_VECTOR_MAPPING(irq)
#else #else
/** /**
* @brief Convert a statically connected IRQ to its interrupt vector number * @brief Convert a statically connected IRQ to its interrupt vector number
@ -393,9 +398,6 @@ static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
_do_irq_unlock(); _do_irq_unlock();
} }
/** interrupt/exception/error related definitions */
typedef void (*NANO_EOI_GET_FUNC) (void *);
/** /**
* The NANO_SOFT_IRQ macro must be used as the value for the @a irq parameter * The NANO_SOFT_IRQ macro must be used as the value for the @a irq parameter
* to NANO_CPU_INT_REGSITER when connecting to an interrupt that does not * to NANO_CPU_INT_REGSITER when connecting to an interrupt that does not
@ -453,17 +455,6 @@ extern FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
/** Dummy ESF for fatal errors that would otherwise not have an ESF */ /** Dummy ESF for fatal errors that would otherwise not have an ESF */
extern const NANO_ESF _default_esf; extern const NANO_ESF _default_esf;
/**
*
* @brief Program interrupt controller
*
* This routine programs the interrupt controller with the given vector
* based on the given IRQ parameter and triggering flags.
* Implicitly called by IRQ_CONNECT().
*
*/
extern void _SysIntVecProgram(unsigned int vector, unsigned int irq, uint32_t flags);
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
/* reboot through Reset Control Register (I/O port 0xcf9) */ /* reboot through Reset Control Register (I/O port 0xcf9) */

116
include/arch/x86/irq_controller.h Normal file
View file

@ -0,0 +1,116 @@
/*
* Copyright (c) 2016 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Abstraction layer for x86 interrupt controllers
*
* Most x86 just support APIC. However we are starting to see design
* variants such as MVIC or APICs with reduced feature sets. This
* interface provides a layer of abstraction between the core arch code
* and the interrupt controller implementation for x86
*/
#ifndef IRQ_CONTROLLER_H
#define IRQ_CONTROLLER_H
#ifdef CONFIG_MVIC
#include <drivers/mvic.h>
#else
#include <drivers/sysapic.h>
#endif
/* Triggering flags abstraction layer.
* If a particular set of triggers is not supported, leave undefined
*/
#define IRQ_TRIGGER_EDGE _IRQ_TRIGGER_EDGE
#define IRQ_TRIGGER_LEVEL _IRQ_TRIGGER_LEVEL
#define IRQ_POLARITY_HIGH _IRQ_POLARITY_HIGH
#define IRQ_POLARITY_LOW _IRQ_POLARITY_LOW
#ifndef _ASMLANGUAGE
#if CONFIG_X86_FIXED_IRQ_MAPPING
/**
* @brief Return fixed mapping for an IRQ
*
* @param irq Interrupt line
* @return Vector this interrupt has been assigned to
*/
#define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) \
__IRQ_CONTROLLER_VECTOR_MAPPING(irq)
#endif
/**
*
* @brief Program an interrupt
*
* This function sets the triggering options for an IRQ and also associates
* the IRQ with its vector in the IDT. This does not enable the interrupt
* line, it will be left masked.
*
* The flags parameter is limited to the IRQ_TRIGGER_* defines above. In
* addition, not all interrupt controllers support all flags.
*
* @param irq Virtualized IRQ
* @param vector Vector Number
* @param flags Interrupt flags
*
* @returns: N/A
*/
static inline void _irq_controller_irq_config(unsigned int vector,
unsigned int irq, uint32_t flags)
{
__irq_controller_irq_config(vector, irq, flags);
}
/**
* @brief Return the vector of the currently in-service ISR
*
* This function should be called in interrupt context.
* It is not expected for this function to reveal the identity of
* vectors triggered by a CPU exception or 'int' instruction.
*
* @return the vector of the interrupt that is currently being processed.
*/
static inline int _irq_controller_isr_vector_get(void)
{
return __irq_controller_isr_vector_get();
}
#else /* _ASMLANGUAGE */
/**
* @brief Send EOI to the interrupt controller
*
* This macro is used by the core interrupt handling code. Interrupts
* will be locked when this gets called and will not be unlocked until
* 'iret' has been issued.
*
* This macro is used in exactly one spot in intStub.S, in _IntExitWithEoi.
* At the time this is called, implementations are free to use the caller-
* saved registers eax, edx, ecx for their own purposes with impunity but
* need to preserve all callee-saved registers.
*/
.macro _irq_controller_eoi
__irq_controller_eoi
.endm
#endif /* _ASMLANGUAGE */
#endif /* IRQ_CONTROLLER_H */

7
include/arch/x86/linker-common-sections.h
View file

@ -48,13 +48,11 @@
*/ */
#define _LINKER #define _LINKER
#define _ASMLANGUAGE /* Needed to include mmustructs.h */
#define _ASMLANGUAGE
#include <linker-defs.h> #include <linker-defs.h>
#include <offsets.h> #include <offsets.h>
#include <misc/util.h> #include <misc/util.h>
#include <arch/cpu.h>
#define MMU_PAGE_SIZE KB(4) #define MMU_PAGE_SIZE KB(4)
#include <linker-tool.h> #include <linker-tool.h>
@ -150,8 +148,7 @@ SECTIONS
*(.gnu.linkonce.r.*) *(.gnu.linkonce.r.*)
IDT_MEMORY IDT_MEMORY
#ifndef CONFIG_MVIC #ifndef CONFIG_X86_FIXED_IRQ_MAPPING
/* MVIC has fixed mapping, don't need this table */
IRQ_TO_INTERRUPT_VECTOR_MEMORY IRQ_TO_INTERRUPT_VECTOR_MEMORY
#endif /* CONFIG_MVIC */ #endif /* CONFIG_MVIC */
KEXEC_PGALIGN_PAD(MMU_PAGE_SIZE) KEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)

19
include/drivers/loapic.h
View file

@ -60,30 +60,11 @@ extern "C" {
extern void _loapic_int_vec_set(unsigned int irq, unsigned int vector); extern void _loapic_int_vec_set(unsigned int irq, unsigned int vector);
extern void _loapic_irq_enable(unsigned int irq); extern void _loapic_irq_enable(unsigned int irq);
extern void _loapic_irq_disable(unsigned int irq); extern void _loapic_irq_disable(unsigned int irq);
extern void _loapic_enable(void);
extern void _loapic_disable(void);
extern int _loapic_isr_vector_get(void);
#if CONFIG_EOI_FORWARDING_BUG #if CONFIG_EOI_FORWARDING_BUG
extern void _lakemont_eoi(void); extern void _lakemont_eoi(void);
#endif #endif
/**
*
* @brief send EOI (End Of Interrupt) signal to Local APIC
*
* This routine sends an EOI signal to the Local APIC's interrupting source.
*
* @return N/A
*/
static inline void _loapic_eoi(void)
{
#if CONFIG_EOI_FORWARDING_BUG
_lakemont_eoi();
#else
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
#endif
}
#endif /* _ASMLANGUAGE */ #endif /* _ASMLANGUAGE */
#ifdef __cplusplus #ifdef __cplusplus

79
include/drivers/mvic.h
View file

@ -14,31 +14,66 @@
* limitations under the License. * limitations under the License.
*/ */
/** #ifndef MVIC_H
* @brief Quark D2000 Interrupt Controller (MVIC) public APIs #define MVIC_H
*
* MVIC interrupt controller driver exports the same APIs as the standard #include <arch/cpu.h>
* local apic & IO Apic drivers with the exception that it replaces the init
* routines with a single _mvic_init routine. /* Register defines. A lot of similarities to APIC, but not quite the same */
#define MVIC_TPR 0xFEE00080 /* Task priority register */
#define MVIC_PPR 0xFEE000A0 /* Process priority register */
#define MVIC_EOI 0xFEE000B0 /* End-of-interrupt register */
#define MVIC_SIVR 0xFEE000F0 /* Spurious interrupt vector register */
#define MVIC_ISR 0xFEE00110 /* In-service register */
#define MVIC_IRR 0xFEE00210 /* Interrupt request register */
#define MVIC_LVTTIMER 0xFEE00320 /* Local vector table timer register */
#define MVIC_ICR 0xFEE00380 /* Timer initial count register */
#define MVIC_CCR 0xFEE00390 /* Timer current count register */
#define MVIC_IOREGSEL 0xFEC00000 /* Register select (index) */
#define MVIC_IOWIN 0xFEC00010 /* Register windows (data) */
/* MVIC_LVTTIMER bits */
#define MVIC_LVTTIMER_MASK BIT(16)
#define MVIC_LVTTIMER_PERIODIC BIT(17)
/* MVIC_IOWIN bits */
#define MVIC_IOWIN_TRIGGER_LEVEL BIT(15)
#define MVIC_IOWIN_TRIGGER_EDGE 0
#define MVIC_IOWIN_MASK BIT(16)
#define MVIC_IOWIN_SUPPORTED_BITS_MASK (MVIC_IOWIN_MASK | \
MVIC_IOWIN_TRIGGER_LEVEL)
/* MVIC IOREGSEL register usage defines */
#define MVIC_LOW_NIBBLE_MASK 0x07
#define MVIC_HIGH_NIBBLE_MASK 0x18
#define MVIC_NUM_RTES 32
#define _IRQ_TRIGGER_EDGE MVIC_IOWIN_TRIGGER_EDGE
#define _IRQ_TRIGGER_LEVEL MVIC_IOWIN_TRIGGER_LEVEL
/* MVIC does not support IRQ_POLARITY_HIGH or IRQ_POLARITY_LOW,
* leave undefined
*/ */
#ifndef __INC_MVIC
#define __INC_MVIC
#include <drivers/ioapic.h>
#include <drivers/loapic.h>
#include <init.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE #ifndef _ASMLANGUAGE
extern int _mvic_init(struct device *unused);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus /* Implementation of irq_controller.h interface */
}
#define __IRQ_CONTROLLER_VECTOR_MAPPING(irq) ((irq) + 32)
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
uint32_t flags);
int __irq_controller_isr_vector_get(void);
#else /* _ASMLANGUAGE */
.macro __irq_controller_eoi
xorl %eax, %eax /* zeroes eax */
movl %eax, MVIC_EOI /* tell MVIC the IRQ is handled */
.endm
#endif #endif
#endif /* __INC_MVIC */ #endif /* MVIC_H */

40
include/drivers/sysapic.h
View file

@ -17,28 +17,40 @@
#ifndef __INC_SYS_APIC_H #ifndef __INC_SYS_APIC_H
#define __INC_SYS_APIC_H #define __INC_SYS_APIC_H
#if !defined(LOAPIC_IRQ_BASE) && !defined(LOAPIC_IRQ_COUNT) #include <drivers/ioapic.h>
#include <drivers/loapic.h>
/* Default IA32 system APIC definitions with local APIC IRQs after IO APIC. */ #define _IRQ_TRIGGER_EDGE IOAPIC_EDGE
#define _IRQ_TRIGGER_LEVEL IOAPIC_LEVEL
#define _IRQ_POLARITY_HIGH IOAPIC_HIGH
#define _IRQ_POLARITY_LOW IOAPIC_LOW
#ifndef _ASMLANGUAGE
#define LOAPIC_IRQ_BASE CONFIG_IOAPIC_NUM_RTES #define LOAPIC_IRQ_BASE CONFIG_IOAPIC_NUM_RTES
#define LOAPIC_IRQ_COUNT 6 /* Default to LOAPIC_TIMER to LOAPIC_ERROR */ #define LOAPIC_IRQ_COUNT 6 /* Default to LOAPIC_TIMER to LOAPIC_ERROR */
#define IS_IOAPIC_IRQ(irq) (irq < LOAPIC_IRQ_BASE) /* irq_controller.h interface */
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
uint32_t flags);
#define HARDWARE_IRQ_LIMIT ((LOAPIC_IRQ_BASE + LOAPIC_IRQ_COUNT) - 1) int __irq_controller_isr_vector_get(void);
#else /* _ASMLANGUAGE */
#if CONFIG_EOI_FORWARDING_BUG
.macro __irq_controller_eoi
call _lakemont_eoi
.endm
#else #else
.macro __irq_controller_eoi
xorl %eax, %eax /* zeroes eax */
loapic_eoi_reg = (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
movl %eax, loapic_eoi_reg /* tell LOAPIC the IRQ is handled */
.endm
#endif /* CONFIG_EOI_FORMWARDING_BUG */
/* Assumption for boards that define LOAPIC_IRQ_BASE & LOAPIC_IRQ_COUNT that #endif /* _ASMLANGUAGE */
* local APIC IRQs are within IOAPIC RTE range.
*/
#define IS_IOAPIC_IRQ(irq) ((irq < LOAPIC_IRQ_BASE) || \
(irq >= (LOAPIC_IRQ_BASE + LOAPIC_IRQ_COUNT)))
#define HARDWARE_IRQ_LIMIT (CONFIG_IOAPIC_NUM_RTES - 1)
#endif
#endif /* __INC_SYS_APIC_H */ #endif /* __INC_SYS_APIC_H */