x86: declare internal API for interrupt controllers
Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie
parent
c545e19a00
commit
e98ac235e6
22 changed files with 432 additions and 680 deletions
|
|
@ -30,7 +30,7 @@ config LOAPIC
|
|||
config LOAPIC_BASE_ADDRESS
|
||||
hex "Local APIC Base Address"
|
||||
default 0xFEE00000
|
||||
depends on LOAPIC || MVIC
|
||||
depends on LOAPIC
|
||||
help
|
||||
This option specifies the base address of the Local APIC device.
|
||||
|
||||
|
|
@ -76,7 +76,7 @@ config IOAPIC_DEBUG
|
|||
config IOAPIC_BASE_ADDRESS
|
||||
hex "IO-APIC Base Address"
|
||||
default 0xFEC00000
|
||||
depends on IOAPIC || MVIC
|
||||
depends on IOAPIC
|
||||
help
|
||||
This option specifies the base address of the IO-APIC device.
|
||||
|
||||
|
|
@ -95,6 +95,7 @@ config MVIC
|
|||
bool "Intel Quark D2000 Interrupt Controller (MVIC)"
|
||||
default n
|
||||
depends on X86
|
||||
select X86_FIXED_IRQ_MAPPING
|
||||
help
|
||||
The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is
|
||||
configured by default to support 32 external interrupt lines. Unlike the
|
||||
|
|
@ -102,6 +103,16 @@ config MVIC
|
|||
not programmable. In addition, the priorities of these interrupt
|
||||
lines are also fixed.
|
||||
|
||||
config MVIC_TIMER_IRQ
|
||||
int "IRQ line to use for timer interrupt"
|
||||
range 0 15
|
||||
default 0
|
||||
depends on MVIC
|
||||
help
|
||||
Specify the IRQ line to use for the timer interrupt. This should be
|
||||
an IRQ line unused by any hardware. If nested interrupts are enabled,
|
||||
higher interrupt lines have priority.
|
||||
|
||||
config ARCV2_INTERRUPT_UNIT
|
||||
bool "ARCv2 Interrupt Unit"
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -1,8 +1,7 @@
|
|||
obj-${CONFIG_PIC_DISABLE} = i8259.o
|
||||
|
||||
obj-$(CONFIG_LOAPIC)$(CONFIG_MVIC) += system_apic.o
|
||||
obj-$(CONFIG_MVIC) += mvic.o
|
||||
obj-$(CONFIG_LOAPIC) += loapic_intr.o
|
||||
obj-$(CONFIG_LOAPIC) += loapic_intr.o system_apic.o
|
||||
obj-$(CONFIG_IOAPIC) += ioapic_intr.o
|
||||
obj-$(CONFIG_LOAPIC_SPURIOUS_VECTOR) += loapic_spurious.o
|
||||
|
||||
|
|
|
|||
|
|
@ -208,14 +208,14 @@ uint32_t loapic_suspend_buf[LOPIC_SUSPEND_BITS_REQD / 32] = {0};
|
|||
*
|
||||
*/
|
||||
|
||||
int _loapic_init(struct device *unused)
|
||||
static int _loapic_init(struct device *unused)
|
||||
{
|
||||
ARG_UNUSED(unused);
|
||||
int32_t loApicMaxLvt; /* local APIC Max LVT */
|
||||
|
||||
/* enable the Local APIC */
|
||||
|
||||
_loapic_enable();
|
||||
sys_write32(sys_read32(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR)
|
||||
| LOAPIC_ENABLE, CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR);
|
||||
|
||||
loApicMaxLvt = (*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_VER) &
|
||||
LOAPIC_MAXLVT_MASK) >> 16;
|
||||
|
|
@ -262,60 +262,29 @@ int _loapic_init(struct device *unused)
|
|||
|
||||
#if CONFIG_LOAPIC_SPURIOUS_VECTOR
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) =
|
||||
(*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) & 0xFFFFFF00)
|
||||
(*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR)
|
||||
& 0xFFFFFF00)
|
||||
| (LOAPIC_SPURIOUS_VECTOR_ID & 0xFF);
|
||||
#endif
|
||||
|
||||
/* discard a pending interrupt if any */
|
||||
_loapic_eoi();
|
||||
#if CONFIG_EOI_FORWARDING_BUG
|
||||
_lakemont_eoi();
|
||||
#else
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Enable the Local xAPIC
|
||||
*
|
||||
* This routine enables the Local xAPIC.
|
||||
*
|
||||
* @return N/A
|
||||
*/
|
||||
|
||||
void _loapic_enable(void)
|
||||
{
|
||||
int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
|
||||
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) |= LOAPIC_ENABLE;
|
||||
|
||||
irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Disable the Local xAPIC
|
||||
*
|
||||
* This routine disables the Local xAPIC.
|
||||
*
|
||||
* @return N/A
|
||||
*/
|
||||
|
||||
void _loapic_disable(void)
|
||||
{
|
||||
int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
|
||||
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) &=
|
||||
~LOAPIC_ENABLE;
|
||||
|
||||
irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Set the vector field in the specified RTE
|
||||
*
|
||||
* This routine is utilized by the interrupt controller's _SysIntVecAlloc()
|
||||
* routine (which exists to support the irq_connect_dynamic() API). Once
|
||||
* a vector has been allocated, this routine is invoked to update the LVT
|
||||
* entry associated with <irq> with the vector.
|
||||
* This routine is utilized by the interrupt controller's
|
||||
* _interrupt_vector_allocate() routine (which exists to support the
|
||||
* irq_connect_dynamic() API). Once a vector has been allocated, this routine
|
||||
* is invoked to update the LVT entry associated with <irq> with the vector.
|
||||
*
|
||||
* @return N/A
|
||||
*/
|
||||
|
|
@ -439,7 +408,7 @@ void _loapic_irq_disable(unsigned int irq)
|
|||
*
|
||||
* @return The vector of the interrupt that is currently being processed.
|
||||
*/
|
||||
int _loapic_isr_vector_get(void)
|
||||
int __irq_controller_isr_vector_get(void)
|
||||
{
|
||||
int pReg, block;
|
||||
|
||||
|
|
@ -490,7 +459,7 @@ static int loapic_suspend(struct device *port, int pm_policy)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int loapic_resume(struct device *port, int pm_policy)
|
||||
static int loapic_resume(struct device *port, int pm_policy)
|
||||
{
|
||||
int loapic_irq;
|
||||
|
||||
|
|
|
|||
|
|
@ -45,398 +45,24 @@
|
|||
#include <nanokernel.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <misc/__assert.h>
|
||||
#include <misc/util.h>
|
||||
#include <init.h>
|
||||
#include <arch/x86/irq_controller.h>
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#include <toolchain.h>
|
||||
#include <sections.h>
|
||||
|
||||
#include <drivers/ioapic.h> /* IO APIC public API declarations. */
|
||||
#include <drivers/loapic.h> /* Local APIC public API declarations.*/
|
||||
|
||||
/* defines */
|
||||
|
||||
/* IO APIC direct register offsets */
|
||||
|
||||
#define IOAPIC_IND 0x00 /* Index Register - MVIC IOREGSEL register */
|
||||
#define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
|
||||
|
||||
/* MVIC IOREGSEL register usage defines */
|
||||
#define MVIC_LOW_NIBBLE_MASK 0x07
|
||||
#define MVIC_HIGH_NIBBLE_MASK 0x18
|
||||
|
||||
/* MVIC Local APIC Vector Table Bits */
|
||||
|
||||
#define LOAPIC_VECTOR 0x000000ff /* vectorNo */
|
||||
|
||||
/* MVIC Local APIC Spurious-Interrupt Register Bits */
|
||||
|
||||
#define LOAPIC_ENABLE 0x100 /* APIC Enabled */
|
||||
|
||||
#define LOAPIC_MVIC_ISR 0x110 /* MVIC In-Service Register offset */
|
||||
|
||||
/* forward declarations */
|
||||
|
||||
static void _mvic_rte_set(unsigned int irq, uint32_t value);
|
||||
static uint32_t _mvic_rte_get(unsigned int irq);
|
||||
static void _mvic_rte_update(unsigned int irq, uint32_t value,
|
||||
uint32_t mask);
|
||||
|
||||
/*
|
||||
* The functions irq_enable() and irq_disable() are implemented
|
||||
* in the platforms that incorporate this interrupt controller driver due to the
|
||||
* IRQ virtualization imposed by the platform.
|
||||
*/
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief initialize the MVIC IO APIC and local APIC register sets.
|
||||
*
|
||||
* This routine initializes the Quark D2000 Interrupt Controller (MVIC).
|
||||
* This routine replaces the standard Local APIC / IO APIC init routines.
|
||||
*
|
||||
* @returns: N/A
|
||||
*/
|
||||
int _mvic_init(struct device *unused)
|
||||
static inline uint32_t compute_ioregsel(unsigned int irq)
|
||||
{
|
||||
ARG_UNUSED(unused);
|
||||
int32_t ix; /* Interrupt line register index */
|
||||
uint32_t rteValue; /* value to copy into interrupt line register */
|
||||
|
||||
/*
|
||||
* The platform must define the CONFIG_IOAPIC_NUM_RTES macro to indicate the number
|
||||
* of redirection table entries supported by the IOAPIC on the board.
|
||||
*
|
||||
|
||||
* By default mask all interrupt lines and set default sensitivity to edge.
|
||||
*
|
||||
*/
|
||||
|
||||
rteValue = IOAPIC_EDGE | IOAPIC_INT_MASK;
|
||||
|
||||
for (ix = 0; ix < CONFIG_IOAPIC_NUM_RTES; ix++) {
|
||||
_mvic_rte_set(ix, rteValue);
|
||||
}
|
||||
|
||||
/* enable the MVIC Local APIC */
|
||||
|
||||
_loapic_enable();
|
||||
|
||||
/* reset the TPR, and TIMER_ICR */
|
||||
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TPR) = (int)0x0;
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_ICR) = (int)0x0;
|
||||
|
||||
/* program Local Vector Table for the Virtual Wire Mode */
|
||||
|
||||
/* lock the MVIC timer interrupt, set which IRQ line should be
|
||||
* used for timer interrupts (this is unlike LOAPIC where the
|
||||
* vector is programmed instead).
|
||||
*/
|
||||
__ASSERT_NO_MSG(CONFIG_LOAPIC_TIMER_IRQ <= 15);
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER) =
|
||||
LOAPIC_LVT_MASKED | CONFIG_LOAPIC_TIMER_IRQ;
|
||||
|
||||
/* discard a pending interrupt if any */
|
||||
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Send EOI (End Of Interrupt) signal to IO APIC
|
||||
*
|
||||
* This routine sends an EOI signal to the IO APIC's interrupting source.
|
||||
*
|
||||
* All line interrupts on Quark D2000 are EOI'ed with local APIC EOI register.
|
||||
*
|
||||
* @param irq INT number to send EOI
|
||||
*
|
||||
* @returns: N/A
|
||||
*/
|
||||
void _ioapic_eoi(unsigned int irq)
|
||||
{
|
||||
_loapic_eoi();
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Get EOI (End Of Interrupt) information
|
||||
*
|
||||
* This routine returns EOI signalling information for a specific IRQ.
|
||||
*
|
||||
* @param irq INTIN number of interest
|
||||
* @param argRequired ptr to "argument required" result area
|
||||
* @param arg ptr to "argument value" result area
|
||||
*
|
||||
* @returns: address of routine to be called to signal EOI;
|
||||
* as a side effect, also passes back indication if routine requires
|
||||
* an interrupt vector argument and what the argument value should be
|
||||
*/
|
||||
void *_ioapic_eoi_get(unsigned int irq, char *argRequired, void **arg)
|
||||
{
|
||||
|
||||
/* indicate that an argument to the EOI handler is required */
|
||||
|
||||
*argRequired = 1;
|
||||
|
||||
/*
|
||||
* The parameter to the ioApicIntEoi() routine is the vector programmed
|
||||
* into the redirection table. The platform _SysIntVecAlloc() routine
|
||||
* must invoke _IoApicIntEoiGet() after _IoApicRedVecSet() to ensure the
|
||||
* redirection table contains the desired interrupt vector.
|
||||
*
|
||||
* Vectors fixed on this CPU Arch, no memory location on this CPU
|
||||
* arch with this information.
|
||||
*/
|
||||
|
||||
*arg = NULL;
|
||||
|
||||
|
||||
/* lo eoi always used on this CPU arch. */
|
||||
|
||||
return _loapic_eoi;
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Enable a specified APIC interrupt input line
|
||||
*
|
||||
* This routine enables a specified APIC interrupt input line.
|
||||
*
|
||||
* @param irq INTIN number to enable
|
||||
*
|
||||
* @returns: N/A
|
||||
*/
|
||||
void _ioapic_irq_enable(unsigned int irq)
|
||||
{
|
||||
_mvic_rte_update(irq, 0, IOAPIC_INT_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief disable a specified APIC interrupt input line
|
||||
*
|
||||
* This routine disables a specified APIC interrupt input line.
|
||||
*
|
||||
* @param irq INTIN number to disable
|
||||
*
|
||||
* @returns: N/A
|
||||
*/
|
||||
void _ioapic_irq_disable(unsigned int irq)
|
||||
{
|
||||
_mvic_rte_update(irq, IOAPIC_INT_MASK, IOAPIC_INT_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Programs Rte interrupt line register.
|
||||
*
|
||||
* Always mask interrupt as part of programming like standard IOAPIC
|
||||
* version of this routine.
|
||||
* Vector is fixed by this HW and is unused.
|
||||
* Or in flags for trigger bit.
|
||||
*
|
||||
* @param irq Virtualized IRQ
|
||||
* @param vector Vector Number
|
||||
* @param flags Interrupt flags
|
||||
*
|
||||
* @returns: N/A
|
||||
*/
|
||||
void _ioapic_irq_set(unsigned int irq, unsigned int vector, uint32_t flags)
|
||||
{
|
||||
uint32_t rteValue; /* value to copy into Rte register */
|
||||
|
||||
ARG_UNUSED(vector);
|
||||
|
||||
rteValue = IOAPIC_INT_MASK | flags;
|
||||
_mvic_rte_set(irq, rteValue);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief program interrupt vector for specified irq
|
||||
*
|
||||
* Fixed vector on this HW. Nothing to do.
|
||||
*
|
||||
* @param irq Interrupt number
|
||||
* @param vector Vector number
|
||||
*
|
||||
* @returns: N/A
|
||||
*/
|
||||
void _ioapic_int_vec_set(unsigned int irq, unsigned int vector)
|
||||
{
|
||||
ARG_UNUSED(irq);
|
||||
ARG_UNUSED(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Enable the MVIC Local APIC
|
||||
*
|
||||
* This routine enables the MVIC Local APIC.
|
||||
*
|
||||
* @returns: N/A
|
||||
*/
|
||||
void _loapic_enable(void)
|
||||
{
|
||||
int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
|
||||
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) |= LOAPIC_ENABLE;
|
||||
|
||||
irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Disable the MVIC Local APIC.
|
||||
*
|
||||
* This routine disables the MVIC Local APIC.
|
||||
*
|
||||
* @returns: N/A
|
||||
*/
|
||||
void _loapic_disable(void)
|
||||
{
|
||||
int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
|
||||
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) &= ~LOAPIC_ENABLE;
|
||||
|
||||
irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Set the vector field in the specified RTE
|
||||
*
|
||||
* Fixed vectors on this HW. Nothing to do.
|
||||
*
|
||||
* @param irq IRQ number of the interrupt
|
||||
* @param vector vector to copy into the LVT
|
||||
*
|
||||
* @returns N/A
|
||||
*/
|
||||
void _loapic_int_vec_set(unsigned int irq, unsigned int vector)
|
||||
{
|
||||
ARG_UNUSED(irq);
|
||||
ARG_UNUSED(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief enable an individual LOAPIC interrupt (IRQ)
|
||||
*
|
||||
* This routine clears the interrupt mask bit in the LVT for the specified IRQ
|
||||
*
|
||||
* @param irq IRQ number of the interrupt
|
||||
*
|
||||
* @returns N/A
|
||||
*/
|
||||
void _loapic_irq_enable(unsigned int irq)
|
||||
{
|
||||
volatile int *pLvt; /* pointer to local vector table */
|
||||
int32_t oldLevel; /* previous interrupt lock level */
|
||||
|
||||
/*
|
||||
* irq is actually an index to local APIC LVT register.
|
||||
* ASSERT if out of range for MVIC implementation.
|
||||
*/
|
||||
__ASSERT_NO_MSG(irq < LOAPIC_IRQ_COUNT);
|
||||
|
||||
/*
|
||||
* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
|
||||
* and ths assumption concerning LVT spacing.
|
||||
*/
|
||||
|
||||
pLvt = (volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER +
|
||||
(irq * LOAPIC_LVT_REG_SPACING));
|
||||
|
||||
/* clear the mask bit in the LVT */
|
||||
|
||||
oldLevel = irq_lock();
|
||||
*pLvt = *pLvt & ~LOAPIC_LVT_MASKED;
|
||||
irq_unlock(oldLevel);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief disable an individual LOAPIC interrupt (IRQ)
|
||||
*
|
||||
* This routine clears the interrupt mask bit in the LVT for the specified IRQ
|
||||
*
|
||||
* @param irq IRQ number of the interrupt
|
||||
*
|
||||
* @returns N/A
|
||||
*/
|
||||
void _loapic_irq_disable(unsigned int irq)
|
||||
{
|
||||
volatile int *pLvt; /* pointer to local vector table */
|
||||
int32_t oldLevel; /* previous interrupt lock level */
|
||||
|
||||
/*
|
||||
* irq is actually an index to local APIC LVT register.
|
||||
* ASSERT if out of range for MVIC implementation.
|
||||
*/
|
||||
__ASSERT_NO_MSG(irq < LOAPIC_IRQ_COUNT);
|
||||
|
||||
/*
|
||||
* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
|
||||
* and ths assumption concerning LVT spacing.
|
||||
*/
|
||||
|
||||
pLvt = (volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER +
|
||||
(irq * LOAPIC_LVT_REG_SPACING));
|
||||
|
||||
/* set the mask bit in the LVT */
|
||||
|
||||
oldLevel = irq_lock();
|
||||
*pLvt = *pLvt | LOAPIC_LVT_MASKED;
|
||||
irq_unlock(oldLevel);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief read a 32 bit MVIC IO APIC register
|
||||
*
|
||||
* @param irq INTIN number
|
||||
*
|
||||
* @returns register value
|
||||
*/
|
||||
static uint32_t _mvic_rte_get(unsigned int irq)
|
||||
{
|
||||
uint32_t value; /* value */
|
||||
int key; /* interrupt lock level */
|
||||
volatile unsigned int *rte;
|
||||
volatile unsigned int *index;
|
||||
unsigned int low_nibble;
|
||||
unsigned int high_nibble;
|
||||
|
||||
index = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND);
|
||||
rte = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA);
|
||||
|
||||
/* Set index in the IOREGSEL */
|
||||
__ASSERT(irq < CONFIG_IOAPIC_NUM_RTES, "INVL");
|
||||
__ASSERT(irq < MVIC_NUM_RTES, "invalid irq line %d", irq);
|
||||
|
||||
low_nibble = ((irq & MVIC_LOW_NIBBLE_MASK) << 0x1);
|
||||
high_nibble = ((irq & MVIC_HIGH_NIBBLE_MASK) << 0x2);
|
||||
|
||||
/* lock interrupts to ensure indirect addressing works "atomically" */
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
*(index) = high_nibble | low_nibble;
|
||||
value = *(rte);
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
return value;
|
||||
return low_nibble | high_nibble;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief write to 32 bit MVIC IO APIC register
|
||||
|
|
@ -449,30 +75,23 @@ static uint32_t _mvic_rte_get(unsigned int irq)
|
|||
static void _mvic_rte_set(unsigned int irq, uint32_t value)
|
||||
{
|
||||
int key; /* interrupt lock level */
|
||||
volatile unsigned int *rte;
|
||||
volatile unsigned int *index;
|
||||
unsigned int low_nibble;
|
||||
unsigned int high_nibble;
|
||||
uint32_t regsel;
|
||||
|
||||
index = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND);
|
||||
rte = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA);
|
||||
__ASSERT(!(value & ~MVIC_IOWIN_SUPPORTED_BITS_MASK),
|
||||
"invalid IRQ flags %x for irq %d", value, irq);
|
||||
|
||||
/* Set index in the IOREGSEL */
|
||||
__ASSERT(irq < CONFIG_IOAPIC_NUM_RTES, "INVL");
|
||||
|
||||
low_nibble = ((irq & MVIC_LOW_NIBBLE_MASK) << 0x1);
|
||||
high_nibble = ((irq & MVIC_HIGH_NIBBLE_MASK) << 0x2);
|
||||
regsel = compute_ioregsel(irq);
|
||||
|
||||
/* lock interrupts to ensure indirect addressing works "atomically" */
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
*(index) = high_nibble | low_nibble;
|
||||
*(rte) = (value & IOAPIC_LO32_RTE_SUPPORTED_MASK);
|
||||
sys_write32(regsel, MVIC_IOREGSEL);
|
||||
sys_write32(value, MVIC_IOWIN);
|
||||
|
||||
irq_unlock(key);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief modify interrupt line register.
|
||||
|
|
@ -485,9 +104,106 @@ static void _mvic_rte_set(unsigned int irq, uint32_t value)
|
|||
*/
|
||||
static void _mvic_rte_update(unsigned int irq, uint32_t value, uint32_t mask)
|
||||
{
|
||||
_mvic_rte_set(irq, (_mvic_rte_get(irq) & ~mask) | (value & mask));
|
||||
int key;
|
||||
uint32_t regsel, old_value, updated_value;
|
||||
|
||||
__ASSERT(!(value & ~MVIC_IOWIN_SUPPORTED_BITS_MASK),
|
||||
"invalid IRQ flags %x for irq %d", value, irq);
|
||||
|
||||
regsel = compute_ioregsel(irq);
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
sys_write32(regsel, MVIC_IOREGSEL);
|
||||
|
||||
old_value = sys_read32(MVIC_IOWIN);
|
||||
updated_value = (old_value & ~mask) | (value & mask);
|
||||
sys_write32(updated_value, MVIC_IOWIN);
|
||||
|
||||
irq_unlock(key);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief initialize the MVIC IO APIC and local APIC register sets.
|
||||
*
|
||||
* This routine initializes the Quark D2000 Interrupt Controller (MVIC).
|
||||
* This routine replaces the standard Local APIC / IO APIC init routines.
|
||||
*
|
||||
* @returns: N/A
|
||||
*/
|
||||
static int _mvic_init(struct device *unused)
|
||||
{
|
||||
ARG_UNUSED(unused);
|
||||
int i;
|
||||
|
||||
/* By default mask all interrupt lines */
|
||||
for (i = 0; i < MVIC_NUM_RTES; i++) {
|
||||
_mvic_rte_set(i, MVIC_IOWIN_MASK);
|
||||
}
|
||||
|
||||
/* reset the task priority and timer initial count registers */
|
||||
sys_write32(0, MVIC_TPR);
|
||||
sys_write32(0, MVIC_ICR);
|
||||
|
||||
/* Initialize and mask the timer interrupt.
|
||||
* Bits 0-3 program the interrupt line number we will use
|
||||
* for the timer interrupt.
|
||||
*/
|
||||
__ASSERT(CONFIG_MVIC_TIMER_IRQ < 16,
|
||||
"Bad irq line %d chosen for timer irq", CONFIG_MVIC_TIMER_IRQ);
|
||||
sys_write32(MVIC_LVTTIMER_MASK | CONFIG_MVIC_TIMER_IRQ, MVIC_LVTTIMER);
|
||||
|
||||
/* discard a pending interrupt if any */
|
||||
sys_write32(0, MVIC_EOI);
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
SYS_INIT(_mvic_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|
||||
|
||||
|
||||
void _arch_irq_enable(unsigned int irq)
|
||||
{
|
||||
if (irq == CONFIG_MVIC_TIMER_IRQ) {
|
||||
sys_write32(sys_read32(MVIC_LVTTIMER) & ~MVIC_LVTTIMER_MASK,
|
||||
MVIC_LVTTIMER);
|
||||
} else {
|
||||
_mvic_rte_update(irq, 0, MVIC_IOWIN_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void _arch_irq_disable(unsigned int irq)
|
||||
{
|
||||
if (irq == CONFIG_MVIC_TIMER_IRQ) {
|
||||
sys_write32(sys_read32(MVIC_LVTTIMER) | MVIC_LVTTIMER_MASK,
|
||||
MVIC_LVTTIMER);
|
||||
} else {
|
||||
_mvic_rte_update(irq, MVIC_IOWIN_MASK, MVIC_IOWIN_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
|
||||
uint32_t flags)
|
||||
{
|
||||
ARG_UNUSED(vector);
|
||||
|
||||
/* Vector argument always ignored. There are no triggering options
|
||||
* for the timer, so nothing to do at all for that case. Other I/O
|
||||
* interrupts need their triggering set
|
||||
*/
|
||||
if (irq != CONFIG_MVIC_TIMER_IRQ) {
|
||||
_mvic_rte_set(irq, MVIC_IOWIN_MASK | flags);
|
||||
} else {
|
||||
__ASSERT(flags == 0,
|
||||
"Timer interrupt cannot have triggering flags set");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Find the currently executing interrupt vector, if any
|
||||
*
|
||||
|
|
@ -505,12 +221,11 @@ static void _mvic_rte_update(unsigned int irq, uint32_t value, uint32_t mask)
|
|||
*
|
||||
* @return The vector of the interrupt that is currently being processed.
|
||||
*/
|
||||
int _loapic_isr_vector_get(void)
|
||||
int __irq_controller_isr_vector_get(void)
|
||||
{
|
||||
/* pointer to ISR vector table */
|
||||
volatile int *pReg;
|
||||
/* In-service register value */
|
||||
int isr;
|
||||
|
||||
pReg = (volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_MVIC_ISR);
|
||||
|
||||
return 32 + (find_msb_set(*pReg) - 1);
|
||||
isr = sys_read32(MVIC_ISR);
|
||||
return 32 + (find_msb_set(isr) - 1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
#include <drivers/sysapic.h>
|
||||
#include <irq.h>
|
||||
|
||||
#define IS_IOAPIC_IRQ(irq) (irq < LOAPIC_IRQ_BASE)
|
||||
#define HARDWARE_IRQ_LIMIT ((LOAPIC_IRQ_BASE + LOAPIC_IRQ_COUNT) - 1)
|
||||
|
||||
/**
|
||||
*
|
||||
|
|
@ -52,8 +54,11 @@
|
|||
* @param flags interrupt flags
|
||||
*
|
||||
*/
|
||||
void _SysIntVecProgram(unsigned int vector, unsigned int irq, uint32_t flags)
|
||||
void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
|
||||
uint32_t flags)
|
||||
{
|
||||
__ASSERT(irq >= 0 && irq <= HARDWARE_IRQ_LIMIT, "invalid irq line");
|
||||
|
||||
if (IS_IOAPIC_IRQ(irq)) {
|
||||
_ioapic_irq_set(irq, vector, flags);
|
||||
} else {
|
||||
|
|
@ -73,7 +78,7 @@ void _SysIntVecProgram(unsigned int vector, unsigned int irq, uint32_t flags)
|
|||
*
|
||||
* The irq_enable() routine is provided by the interrupt controller driver due
|
||||
* to the IRQ virtualization that is performed by this platform. See the
|
||||
* comments in _SysIntVecAlloc() for more information regarding IRQ
|
||||
* comments in _interrupt_vector_allocate() for more information regarding IRQ
|
||||
* virtualization.
|
||||
*
|
||||
* @return N/A
|
||||
|
|
@ -93,7 +98,7 @@ void _arch_irq_enable(unsigned int irq)
|
|||
*
|
||||
* The irq_disable() routine is provided by the interrupt controller driver due
|
||||
* to the IRQ virtualization that is performed by this platform. See the
|
||||
* comments in _SysIntVecAlloc() for more information regarding IRQ
|
||||
* comments in _interrupt_vector_allocate() for more information regarding IRQ
|
||||
* virtualization.
|
||||
*
|
||||
* @return N/A
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue