boards: arm: add efm32gg_sltb009a board

- Add Silabs SLTB009A board
- Add Silabs EFM32GG12B SoC

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>

boards/arm/efm32gg_sltb009a/Kconfig.board

@@ -0,0 +1,8 @@
+# EFM32GG SLTB009A board configuration
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EFM32GG_SLTB009A
+	bool "SiLabs EFM32GG-SLTB009A (Giant Gecko 12)"
+	depends on SOC_SERIES_EFM32GG12B
+	select SOC_PART_NUMBER_EFM32GG12B810F1024GM64

boards/arm/efm32gg_sltb009a/Kconfig.defconfig

@@ -0,0 +1,24 @@
+# EFM32GG SLTB009A default board configuration
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_EFM32GG_SLTB009A
+
+config BOARD
+	string
+	default "efm32gg_sltb009a"
+
+config CMU_HFXO_FREQ
+	default 50000000
+
+config CMU_HFRCO_FREQ
+	default 72000000
+
+config CMU_LFXO_FREQ
+	default 32768
+
+config LOG_BACKEND_SWO_FREQ_HZ
+	default 875000
+	depends on LOG_BACKEND_SWO
+
+endif # BOARD_EFM32GG_SLTB009A

boards/arm/efm32gg_sltb009a/board.cmake

@@ -0,0 +1,5 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=EFM32GG12B810F1024")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.dts

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <silabs/efm32gg12b810f1024gm64.dtsi>
+
+/ {
+	model = "Silicon Labs EFM32GG SLTB009A board";
+	compatible = "silabs,efm32gg_sltb009a";
+
+	chosen {
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		watchdog0 = &wdog0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
+			label = "LED 0";
+		};
+		led1: led_1 {
+			gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>;
+			label = "LED 1";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button0: button_0 {
+			gpios = <&gpiod 5 GPIO_ACTIVE_HIGH>;
+			label = "User Push Button 0";
+		};
+		button1: button_1 {
+			gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
+			label = "User Push Button 1";
+		};
+	};
+};
+
+&usart0 {
+	current-speed = <115200>;
+	location-rx = <GECKO_LOCATION(1) GECKO_PORT_E GECKO_PIN(6)>;
+	location-tx = <GECKO_LOCATION(1) GECKO_PORT_E GECKO_PIN(7)>;
+	status = "okay";
+};
+
+&usart4 {
+	current-speed = <115200>;
+	location-rx = <GECKO_LOCATION(0) GECKO_PORT_B GECKO_PIN(8)>;
+	location-tx = <GECKO_LOCATION(0) GECKO_PORT_B GECKO_PIN(7)>;
+	status = "okay";
+};
+
+&leuart0 {
+	current-speed = <9600>;
+	location-rx = <GECKO_LOCATION(1) GECKO_PORT_B GECKO_PIN(14)>;
+	location-tx = <GECKO_LOCATION(1) GECKO_PORT_B GECKO_PIN(13)>;
+	status = "okay";
+};
+
+&i2c0 {
+	location-sda = <GECKO_LOCATION(4) GECKO_PORT_C GECKO_PIN(0)>;
+	location-scl = <GECKO_LOCATION(4) GECKO_PORT_C GECKO_PIN(1)>;
+	status = "okay";
+};
+
+&i2c1 {
+	location-sda = <GECKO_LOCATION(0) GECKO_PORT_C GECKO_PIN(4)>;
+	location-scl = <GECKO_LOCATION(0) GECKO_PORT_C GECKO_PIN(5)>;
+	status = "okay";
+};
+
+&rtcc0 {
+	prescaler = <1>;
+	status = "okay";
+};
+
+&gpioa {
+	status = "okay";
+	board-controller-enable {
+		// VCOM Isolation. Set PA15 to HIGH to enable VCOM_{RX,TX}.
+		gpio-hog;
+		gpios = <15 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&gpio {
+	location-swo = <0>;
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&gpiod {
+	status = "okay";
+};
+
+&gpioe {
+	status = "okay";
+};
+
+&gpiof {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Set 12Kb of storage at the end of the 2048Kb of flash */
+		storage_partition: partition@1fd000 {
+			label = "storage";
+			reg = <0x001fd000 0x00003000>;
+		};
+	};
+};
+
+&wdog0 {
+	status = "okay";
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&cpu0 {
+	clock-frequency = <72000000>;
+};

boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.yaml

@@ -0,0 +1,15 @@
+identifier: efm32gg_sltb009a
+name: EFM32GG-SLTB009A
+type: mcu
+arch: arm
+ram: 192
+flash: 1024
+toolchain:
+  - zephyr
+supported:
+  - i2c
+  - gpio
+  - nvs
+testing:
+  ignore_tags:
+    - bluetooth

boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_EFM32GG12B=y
+CONFIG_BOARD_EFM32GG_SLTB009A=y
+CONFIG_ARM_MPU=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
+CONFIG_CMU_HFCLK_HFRCO=y

dts/arm/silabs/efm32gg12b.dtsi

@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include "gpio_gecko.h"
+
+/ {
+	chosen {
+		zephyr,entropy = &trng0;
+		zephyr,flash-controller = &msc;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+	       compatible = "mmio-sram";
+	};
+
+	soc {
+		msc: flash-controller@40000000 {
+			compatible = "silabs,gecko-flash-controller";
+			reg = <0x40000000 0x110>;
+			interrupts = <33 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				write-block-size = <4>;
+				erase-block-size = <4096>;
+			};
+		};
+
+		rtcc0: rtcc@40062000 { /* RTCC0 */
+			compatible = "silabs,gecko-rtcc";
+			reg = <0x40062000 0x184>;
+			interrupts = <31 0>;
+			clock-frequency = <32768>;
+			prescaler = <1>;
+			status = "disabled";
+		};
+
+		uart0: uart@40014000 { /* UART0 */
+			compatible = "silabs,gecko-uart";
+			reg = <0x40014000 0x400>;
+			interrupts = <21 0 22 0>;
+			interrupt-names = "rx", "tx";
+			peripheral-id = <0>;
+			status = "disabled";
+		};
+
+		uart1: uart@40014400 { /* UART1 */
+			compatible = "silabs,gecko-uart";
+			reg = <0x40014400 0x400>;
+			interrupts = <23 0 24 0>;
+			interrupt-names = "rx", "tx";
+			peripheral-id = <1>;
+			status = "disabled";
+		};
+
+		usart0: usart@40010000 { /* USART0 */
+			compatible = "silabs,gecko-usart";
+			reg = <0x40010000 0x400>;
+			interrupts = <6 0 7 0>;
+			interrupt-names = "rx", "tx";
+			peripheral-id = <0>;
+			status = "disabled";
+		};
+
+		usart1: usart@40010400 { /* USART1 */
+			compatible = "silabs,gecko-usart";
+			reg = <0x40010400 0x400>;
+			interrupts = <17 0 18 0>;
+			interrupt-names = "rx", "tx";
+			peripheral-id = <1>;
+			status = "disabled";
+		};
+
+		usart2: usart@40010800 { /* USART2 */
+			compatible = "silabs,gecko-usart";
+			reg = <0x40010800 0x400>;
+			interrupts = <19 0 20 0>;
+			interrupt-names = "rx", "tx";
+			peripheral-id = <2>;
+			status = "disabled";
+		};
+
+		usart3: usart@40010c00 { /* USART3 */
+			compatible = "silabs,gecko-usart";
+			reg = <0x40010c00 0x400>;
+			interrupts = <37 0 38 0>;
+			interrupt-names = "rx", "tx";
+			peripheral-id = <3>;
+			status = "disabled";
+		};
+
+		usart4: usart@40011000 { /* USART4 */
+			compatible = "silabs,gecko-usart";
+			reg = <0x40011000 0x400>;
+			interrupts = <39 0 40 0>;
+			interrupt-names = "rx", "tx";
+			peripheral-id = <4>;
+			status = "disabled";
+		};
+
+		leuart0: leuart@4006a000 { /* LEUART0 */
+			compatible = "silabs,gecko-leuart";
+			reg = <0x4006a000 0x400>;
+			interrupts = <25 0>;
+			peripheral-id = <0>;
+			status = "disabled";
+		};
+
+		leuart1: leuart@4006a400 { /* LEUART1 */
+			compatible = "silabs,gecko-leuart";
+			reg = <0x4006a400 0x400>;
+			interrupts = <26 0>;
+			peripheral-id = <1>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@40089000 {
+			compatible = "silabs,gecko-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40089000 0x400>;
+			interrupts = <11 0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@40089400 {
+			compatible = "silabs,gecko-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40089400 0x400>;
+			interrupts = <12 0>;
+			status = "disabled";
+		};
+
+		gpio: gpio@40088400 {
+			compatible = "silabs,gecko-gpio";
+			reg = <0x40088400 0xc00>;
+			interrupts = <3 2 13 2>;
+			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
+
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpioa: gpio@40088000 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x40088000 0x30>;
+				peripheral-id = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+
+			gpiob: gpio@40088030 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x40088030 0x30>;
+				peripheral-id = <1>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+
+			gpioc: gpio@40088060 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x40088060 0x30>;
+				peripheral-id = <2>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+
+			gpiod: gpio@40088090 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x40088090 0x30>;
+				peripheral-id = <3>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+
+			gpioe: gpio@400880c0 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x400880c0 0x30>;
+				peripheral-id = <4>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+
+			gpiof: gpio@400880f0 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x400880f0 0x30>;
+				peripheral-id = <5>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+		};
+
+		trng0: trng@4001d000 {
+			compatible = "silabs,gecko-trng";
+			reg = <0x4001d000 0x400>;
+			interrupts = <57 0>;
+			status = "disabled";
+		};
+
+		wdog0: wdog@40052000 {
+			compatible = "silabs,gecko-wdog";
+			reg = <0x40052000 0x2C>;
+			peripheral-id = <0>;
+			interrupts = <1 0>;
+			status = "disabled";
+		};
+
+		wdog1: wdog@40052400 {
+			compatible = "silabs,gecko-wdog";
+			reg = <0x40052400 0x2C>;
+			peripheral-id = <1>;
+			interrupts = <55 0>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

dts/arm/silabs/efm32gg12b810f1024gm64.dtsi

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/efm32gg12b.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		compatible = "silabs,efm32gg12b", "silabs,efm32gg12",
+			"silabs,efm32", "simple-bus";
+
+		flash-controller@40000000 {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+
+};

soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b

@@ -0,0 +1,7 @@
+# Silicon Labs EFM32GG12B (Giant Gecko) platform configuration options
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config GPIO_GECKO
+	default y
+	depends on GPIO || LOG_BACKEND_SWO

soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.series

@@ -0,0 +1,20 @@
+# EFM32GG12B series configuration options
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_EFM32GG12B
+
+config SOC_SERIES
+	default "efm32gg12b"
+
+config SOC_PART_NUMBER
+	default "EFM32GG12B810F1024GM64" if SOC_PART_NUMBER_EFM32GG12B810F1024GM64
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	default 68
+
+source "soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b"
+
+endif # SOC_SERIES_EFM32GG12B

soc/arm/silabs_exx32/efm32gg12b/Kconfig.series

@@ -0,0 +1,21 @@
+# EFM32GG12B (Giant Gecko) MCU line
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_EFM32GG12B
+	bool "EFM32GG12B Series MCU"
+	select ARM
+	select HAS_SILABS_GECKO
+	select HAS_SWO
+	select CPU_CORTEX_M4
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select SOC_FAMILY_EXX32
+	select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
+	select SOC_GECKO_HAS_HFRCO_FREQRANGE
+	select SOC_GECKO_CMU
+	select SOC_GECKO_EMU
+	select SOC_GECKO_GPIO
+	select SOC_GECKO_TRNG
+	help
+	  Enable support for EFM32 GiantGecko MCU series

soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc

@@ -0,0 +1,7 @@
+# EFM32GG12B (Giant Gecko) MCU line
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_PART_NUMBER_EFM32GG12B810F1024GM64
+	bool
+	depends on SOC_SERIES_EFM32GG12B

soc/arm/silabs_exx32/efm32gg12b/linker.ld

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Linker command/script file
+ *
+ * This is the linker script for both standard images.
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/silabs_exx32/efm32gg12b/soc.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros for the EFM32GG12B SoC family.
+ *
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <zephyr/sys/util.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASMLANGUAGE
+
+#include <em_bus.h>
+#include <em_common.h>
+
+
+#include "soc_pinmap.h"
+#include "../common/soc_gpio.h"
+
+#endif /* !_ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC__H_ */

soc/arm/silabs_exx32/efm32gg12b/soc_pinmap.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/** @file
+ * @brief Silabs EFM32GG12B MCU pin definitions.
+ *
+ * This file contains pin configuration data required by different MCU
+ * modules to correctly configure GPIO controller.
+ */
+
+#ifndef _SILABS_EFM32GG12B_SOC_PINMAP_H_
+#define _SILABS_EFM32GG12B_SOC_PINMAP_H_
+
+#include <zephyr/devicetree.h>
+#include <soc.h>
+#include <em_gpio.h>
+
+#define GPIO_NODE DT_INST(0, silabs_gecko_gpio)
+#if DT_NODE_HAS_PROP(GPIO_NODE, location_swo)
+#define SWO_LOCATION DT_PROP(GPIO_NODE, location_swo)
+#endif
+
+#ifdef CONFIG_GPIO_GECKO
+/* Serial Wire Output (SWO) */
+#if (SWO_LOCATION == 0)
+#define PIN_SWO {gpioPortF, 2, gpioModePushPull, 1}
+#elif (SWO_LOCATION == 1)
+#define PIN_SWO {gpioPortC, 15, gpioModePushPull, 1}
+#elif (SWO_LOCATION == 2)
+#define PIN_SWO {gpioPortD, 1, gpioModePushPull, 1}
+#elif (SWO_LOCATION == 3)
+#define PIN_SWO {gpioPortD, 2, gpioModePushPull, 1}
+#elif (SWO_LOCATION >= 4)
+#error ("Invalid SWO pin location")
+#endif
+#endif /* CONFIG_GPIO_GECKO */
+
+#endif /* _SILABS_EFM32GG12B_SOC_PINMAP_H_ */