From e92fb109712f6199dbd16e6fb909cdc7c97ea3f0 Mon Sep 17 00:00:00 2001 From: Adib Taraben Date: Sun, 27 Apr 2025 17:45:27 +0200 Subject: [PATCH] drivers: hwinfo: add nxp mcxn reset_cause implementation Implementation is specific to the NXP MCXN series. Code mostly copied from hwinfo_mcux_rcm driver. Signed-off-by: Adib Taraben --- drivers/hwinfo/CMakeLists.txt | 1 + drivers/hwinfo/Kconfig | 8 ++ drivers/hwinfo/hwinfo_mcux_mcx_cmc.c | 104 ++++++++++++++++++ modules/hal_nxp/mcux/Kconfig.mcux | 6 + .../mcux/mcux-sdk-ng/drivers/drivers.cmake | 1 + soc/nxp/mcx/mcxn/Kconfig | 1 + 6 files changed, 121 insertions(+) create mode 100644 drivers/hwinfo/hwinfo_mcux_mcx_cmc.c diff --git a/drivers/hwinfo/CMakeLists.txt b/drivers/hwinfo/CMakeLists.txt index 548577d05bf..a74850cfeed 100644 --- a/drivers/hwinfo/CMakeLists.txt +++ b/drivers/hwinfo/CMakeLists.txt @@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_GECKO hwinfo_gecko.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_IMXRT hwinfo_imxrt.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_LITEX hwinfo_litex.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_MAX32 hwinfo_max32.c) +zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_MCX_CMC hwinfo_mcux_mcx_cmc.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_RCM hwinfo_mcux_rcm.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SIM hwinfo_mcux_sim.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC hwinfo_mcux_src.c) diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig index 966f3d399b3..5495eb1bb7d 100644 --- a/drivers/hwinfo/Kconfig +++ b/drivers/hwinfo/Kconfig @@ -79,6 +79,14 @@ config HWINFO_NRF help Enable Nordic NRF hwinfo driver. +config HWINFO_MCUX_MCX_CMC + bool "NXP MCX CMC reset cause" + default y + depends on HAS_MCUX_MCX_CMC + select HWINFO_HAS_DRIVER + help + Enable NXP kinetis mcux CMC hwinfo driver. + config HWINFO_MCUX_RCM bool "NXP kinetis reset cause" default y diff --git a/drivers/hwinfo/hwinfo_mcux_mcx_cmc.c b/drivers/hwinfo/hwinfo_mcux_mcx_cmc.c new file mode 100644 index 00000000000..d6415d79568 --- /dev/null +++ b/drivers/hwinfo/hwinfo_mcux_mcx_cmc.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2025 Adib Taraben + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(hwinfo_cmc, CONFIG_HWINFO_LOG_LEVEL); + +/** + * @brief Translate from CMC reset source mask to Zephyr hwinfo sources mask. + * + * Translate bitmask from MCUX CMC reset source bitmask to Zephyr + * hwinfo reset source bitmask. + * + * @param NXP MCUX CMC reset source mask. + * @retval Zephyr hwinfo reset source mask. + */ +static uint32_t hwinfo_mcux_cmc_xlate_reset_sources(uint32_t sources) +{ + uint32_t mask = 0; + + /* order of tests below according to SRS register definitions */ + if (sources & CMC_SRS_WAKEUP_MASK) { + mask |= RESET_LOW_POWER_WAKE; + } + + if (sources & (CMC_SRS_POR_MASK | CMC_SRS_VBAT_MASK)) { + mask |= RESET_POR; + } + + if (sources & CMC_SRS_VD_MASK) { + mask |= RESET_BROWNOUT; + } + + if (sources & CMC_SRS_PIN_MASK) { + mask |= RESET_PIN; + } + + if (sources & (CMC_SRS_JTAG_MASK | CMC_SRS_DAP_MASK)) { + mask |= RESET_DEBUG; + } + + if (sources & CMC_SRS_SCG_MASK) { + mask |= RESET_CLOCK; + } + + if (sources & (CMC_SRS_WWDT0_MASK | CMC_SRS_WWDT1_MASK)) { + mask |= RESET_WATCHDOG; + } + + if (sources & CMC_SRS_SW_MASK) { + mask |= RESET_SOFTWARE; + } + + if (sources & CMC_SRS_LOCKUP_MASK) { + mask |= RESET_CPU_LOCKUP; + } + + if (sources & (CMC_SRS_CDOG0_MASK | CMC_SRS_CDOG1_MASK)) { + mask |= RESET_WATCHDOG; + } + + if (sources & CMC_SRS_SECVIO_MASK) { + mask |= RESET_SECURITY; + } + + return mask; +} + +int z_impl_hwinfo_get_reset_cause(uint32_t *cause) +{ + const uint32_t sources = CMC_GetStickySystemResetStatus(CMC0); + + *cause = hwinfo_mcux_cmc_xlate_reset_sources(sources); + + LOG_DBG("sources = 0x%08x, cause = 0x%08x", sources, *cause); + + return 0; +} + +int z_impl_hwinfo_clear_reset_cause(void) +{ + const uint32_t sources = CMC_GetStickySystemResetStatus(CMC0); + + CMC_ClearStickySystemResetStatus(CMC0, sources); + + LOG_DBG("sources = 0x%08x", sources); + + return 0; +} + +int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported) +{ + *supported = hwinfo_mcux_cmc_xlate_reset_sources(UINT32_MAX); + + LOG_DBG("supported = 0x%08x", *supported); + + return 0; +} diff --git a/modules/hal_nxp/mcux/Kconfig.mcux b/modules/hal_nxp/mcux/Kconfig.mcux index 885a50d6d64..2452d5707b2 100644 --- a/modules/hal_nxp/mcux/Kconfig.mcux +++ b/modules/hal_nxp/mcux/Kconfig.mcux @@ -343,6 +343,12 @@ config HAS_MCUX_RCM Set if the Reset Control Module (RCM) module is present in the SoC. +config HAS_MCUX_MCX_CMC + bool + help + Set if the Core Mode Controller (CMC) module is present in + the SoC. + config HAS_MCUX_CTIMER bool help diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake index 86778d25db6..98a7365ec6b 100644 --- a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake +++ b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake @@ -104,6 +104,7 @@ set_variable_ifdef(CONFIG_WDT_MCUX_RTWDOG CONFIG_MCUX_COMPONENT_driver.rtw set_variable_ifdef(CONFIG_HAS_MCUX_RDC CONFIG_MCUX_COMPONENT_driver.rdc) set_variable_ifdef(CONFIG_UART_MCUX_IUART CONFIG_MCUX_COMPONENT_driver.iuart) set_variable_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR CONFIG_MCUX_COMPONENT_driver.adc_12b1msps_sar) +set_variable_ifdef(CONFIG_HWINFO_MCUX_MCX_CMC CONFIG_MCUX_COMPONENT_driver.mcx_cmc) set_variable_ifdef(CONFIG_HWINFO_MCUX_SRC CONFIG_MCUX_COMPONENT_driver.src) set_variable_ifdef(CONFIG_HWINFO_MCUX_SIM CONFIG_MCUX_COMPONENT_driver.sim) set_variable_ifdef(CONFIG_HWINFO_MCUX_RCM CONFIG_MCUX_COMPONENT_driver.rcm) diff --git a/soc/nxp/mcx/mcxn/Kconfig b/soc/nxp/mcx/mcxn/Kconfig index 16b7ef6009b..b82262980cf 100644 --- a/soc/nxp/mcx/mcxn/Kconfig +++ b/soc/nxp/mcx/mcxn/Kconfig @@ -9,6 +9,7 @@ config SOC_SERIES_MCXN select HAS_MCUX_FLEXCOMM select CPU_CORTEX_M_HAS_SYSTICK select CPU_CORTEX_M_HAS_DWT + select HAS_MCUX_MCX_CMC config SOC_MCXN947_CPU0 select CPU_CORTEX_M33