soc: added LPC5500 family

SoC implementation for LPC5500 family.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>

soc/arm/nxp_lpc/Kconfig

@@ -19,6 +19,7 @@ source "soc/arm/nxp_lpc/*/Kconfig.soc"
 config SOC_PART_NUMBER
 	string
 	default SOC_PART_NUMBER_LPC54XXX if SOC_SERIES_LPC54XXX
+	default SOC_PART_NUMBER_LPC55XXX if SOC_SERIES_LPC55XXX
 
 	help
 	  This string holds the full part number of the SoC. It is a hidden option

soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2019, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+zephyr_library()
+
+zephyr_library_sources(soc.c)

soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0

@@ -0,0 +1,35 @@
+# Kconfig - NXP LPC55XXX CPU0 platform configuration options
+#
+# Copyright (c) 2019, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_LPC55S69_CPU0
+
+config SOC
+	string
+	default "lpc55S69_cpu0"
+
+if PINMUX
+
+config PINMUX_MCUX_LPC
+	default y
+
+endif # PINMUX
+
+if GPIO
+
+config GPIO_MCUX_LPC
+	default y
+
+endif # GPIO
+
+if SERIAL
+
+config USART_MCUX_LPC
+	default y
+
+endif # SERIAL
+
+endif # SOC_LPC55S69_CPU0

soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu1

@@ -0,0 +1,38 @@
+# Kconfig - NXP LPC55S69 CPU1 platform configuration options
+#
+# Copyright (c) 2019, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_LPC55S69_CPU1
+
+config SOC
+	string
+	default "lpc55S69_cpu1"
+
+if PINMUX
+
+config PINMUX_MCUX_LPC
+	default n
+
+endif # PINMUX
+
+config GPIO
+	default n
+
+if GPIO
+
+config GPIO_MCUX_LPC
+	default n
+
+endif # GPIO
+
+if SERIAL
+
+config USART_MCUX_LPC
+	default n
+
+endif # SERIAL
+
+endif # SOC_LPC55S69_CPU1

soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.series

@@ -0,0 +1,20 @@
+# Kconfig -  LPC55XXX series configuration options
+#
+# Copyright (c) 2019, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_LPC55XXX
+
+config SOC_SERIES
+	default "lpc55xxx"
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	default 60
+
+source "soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lp*"
+
+endif # SOC_SERIES_LPC55XXX

soc/arm/nxp_lpc/lpc55xxx/Kconfig.series

@@ -0,0 +1,14 @@
+# Kconfig - LPC LPC55XXX Series
+#
+# Copyright (c) 2019, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_LPC55XXX
+	bool "LPC5500 Series Family MCU"
+	select HAS_MCUX
+	select SOC_FAMILY_LPC
+	select CPU_CORTEX_M_HAS_SYSTICK
+	help
+	  Enable support for LPC5500 Series MCU series

soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc

@@ -0,0 +1,44 @@
+# Kconfig - LPC LPC55XXX Series
+#
+# Copyright (c) 2019, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "LPC5500 Series MCU Selection"
+depends on SOC_SERIES_LPC55XXX
+
+config SOC_LPC55S69_CPU0
+	bool "SOC_LPC55S69 M33 [CPU 0]"
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+
+config SOC_LPC55S69_CPU1
+	bool "SOC_LPC55S69 M33 [CPU 1]"
+	select CPU_CORTEX_M33
+
+endchoice
+
+if SOC_SERIES_LPC55XXX
+
+config SOC_PART_NUMBER_LPC55S69JBD100
+	bool
+
+config SOC_PART_NUMBER_LPC55S69JET98
+	bool
+
+config SOC_PART_NUMBER_LPC55XXX
+	string
+	default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100
+	default "LPC55S69JET98"  if SOC_PART_NUMBER_LPC55S69JET98
+
+	help
+	  This string holds the full part number of the SoC. It is a hidden
+	  option that you should not set directly. The part number selection
+	  choice defines the default value for this string.
+
+endif # SOC_SERIES_LPC55XXX

soc/arm/nxp_lpc/lpc55xxx/dts_fixup.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2019, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define DT_USART_MCUX_LPC_0_BASE_ADDRESS DT_NXP_LPC_USART_50086000_BASE_ADDRESS
+#define DT_USART_MCUX_LPC_0_BAUD_RATE   DT_NXP_LPC_USART_50086000_CURRENT_SPEED
+#define DT_USART_MCUX_LPC_0_IRQ_PRI DT_NXP_LPC_USART_50086000_IRQ_0_PRIORITY
+#define DT_USART_MCUX_LPC_0_NAME    DT_NXP_LPC_USART_50086000_LABEL
+
+/* End of SoC Level DTS fixup file */

soc/arm/nxp_lpc/lpc55xxx/linker.ld

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Linker command/script file
+ *
+ * This is the linker script for both standard images and XIP images.
+ */
+
+#include <autoconf.h>
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

soc/arm/nxp_lpc/lpc55xxx/soc.c

@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for nxp_lpc55s69 platform
+ *
+ * This module provides routines to initialize and support board-level
+ * hardware for the nxp_lpc55s69 platform.
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+#include <uart.h>
+#include <linker/sections.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+#include <fsl_power.h>
+#include <fsl_clock.h>
+#include <fsl_common.h>
+#include <fsl_device_registers.h>
+
+/**
+ *
+ * @brief Initialize the system clock
+ *
+ * @return N/A
+ *
+ */
+
+static ALWAYS_INLINE void clkInit(void)
+{
+#ifdef CONFIG_SOC_LPC55S69_CPU0
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+	/*!< Ensure FRO is on  */
+	POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
+	/*!< Set up FRO to the 12 MHz, just for sure */
+	CLOCK_SetupFROClocking(12000000U);
+	/*!< Switch to FRO 12MHz first to ensure we can change the clock */
+	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+	/* Enable FRO HF(96MHz) output */
+	CLOCK_SetupFROClocking(96000000U);
+
+	/*!< Set FLASH wait states for core */
+	CLOCK_SetFLASHAccessCyclesForFreq(96000000U);
+
+    /*!< Set up dividers */
+	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+	CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
+
+	/* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+#endif /* CONFIG_SOC_LPC55S69_CPU0 */
+}
+
+/**
+ *
+ * @brief Perform basic hardware initialization
+ *
+ * Initialize the interrupt controller device drivers.
+ * Also initialize the timer device driver, if required.
+ *
+ * @return 0
+ */
+
+static int nxp_lpc55s69_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* old interrupt lock level */
+	unsigned int oldLevel;
+
+	/* disable interrupts */
+	oldLevel = irq_lock();
+
+	z_clearfaults();
+
+	/* Initialize FRO/system clock to 48 MHz */
+	clkInit();
+
+	/*
+	 * install default handler that simply resets the CPU if configured in
+	 * the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	/* restore interrupt state */
+	irq_unlock(oldLevel);
+
+	return 0;
+}
+
+SYS_INIT(nxp_lpc55s69_init, PRE_KERNEL_1, 0);

soc/arm/nxp_lpc/lpc55xxx/soc.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros for the nxp_lpc55s69 platform
+ *
+ * This header file is used to specify and describe board-level aspects for the
+ * 'nxp_lpc55s69' platform.
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASMLANGUAGE
+#include <device.h>
+#include <misc/util.h>
+#include <fsl_common.h>
+#endif /* !_ASMLANGUAGE */
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC10 0x0Au        /*!<@brief Selects pin function 10 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard slew rate mode */
+#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_INPFILT_OFF 0x1000u  /*!<@brief Input filter disabled */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC__H_ */