From e8d2c92abba54f99a6fc907c99a617ecc01bdf4d Mon Sep 17 00:00:00 2001
From: Daniel Leung <daniel.leung@intel.com>
Date: Thu, 21 Feb 2019 15:05:28 -0800
Subject: [PATCH] arch/xtensa: smp: only zero BSS only when boot from CPU #0

Under SMP, the main BSS section only needs to be zero-ed on CPU #0.
Other CPUs should not zero out BSS, or else it may cause CPU #0 to
crash on invalid data.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
---
 arch/xtensa/core/crt1.S | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/xtensa/core/crt1.S b/arch/xtensa/core/crt1.S
index bebecd752da..f1d718609e4 100644
--- a/arch/xtensa/core/crt1.S
+++ b/arch/xtensa/core/crt1.S
@@ -136,6 +136,14 @@ _start:
 	/* Clear a0 again as possible CALLX to __memmap_init changed it. */
 	movi	a0, 0
 # endif
+
+# ifdef CONFIG_SMP
+	/* Only clear BSS when running on core 0 */
+	rsr	a3, PRID
+	extui	a3, a3, 0, 8	/* extract core ID */
+	bnez	a3, .L3zte
+# endif
+
 	/*
 	 *  Clear the BSS (uninitialized data) segments.
 	 *  This code supports multiple zeroed sections (*.bss).