checkpatch: error - trailing_whitespace

Change-Id: I819d13f0d7a23e3a61dcda6a3ced18810b192158
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

arch/arm/platforms/fsl_frdm_k64f/system.c

@@ -308,7 +308,7 @@ static int fsl_frdm_k64f_init(struct device *arg)
 
 	/*
 	 * install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise 
+	 * if configured in the kernel, NOP otherwise
 	 */
 	NMI_INIT();
 

arch/x86/core/float.c

@@ -47,7 +47,7 @@
  *
  * If the nanokernel has been built without SSE instruction support
  * (CONFIG_SSE), the system treats USE_SSE as if it was USE_FP.
- * 
+ *
  * If the nanokernel has been built without floating point resource sharing
  * support (CONFIG_FP_SHARING), the aforementioned APIs and capabilities do not
  * exist.
@@ -60,7 +60,7 @@
  *
  * WARNING
  * The use of floating point instructions by ISRs is not supported by the
- * kernel.  
+ * kernel.
  *
  * INTERNAL
  * If automatic enabling of floating point resource sharing _is not_ configured

arch/x86/core/intconnect.c

@@ -20,22 +20,22 @@
  * DESCRIPTION
  * This module provides routines to manage asynchronous interrupts
  * on the IA-32 architecture.
- * 
+ *
  * This module provides the public routine irq_connect(), the private
  * routine _IntVecSet(), and the support routines _IntVecAlloc(),
  * _IntVecMarkAllocated() and _IntVecMarkFree().
- * 
+ *
  * INTERNAL
  * The _idt_base_address symbol is used to determine the base address of the
  * IDT.  (It is generated by the linker script, and doesn't correspond to an
  * actual global variable.)
- * 
+ *
  * Interrupts are handled by an "interrupt stub" whose code is generated by the
  * system itself.  The stub performs various actions before and after invoking
  * the application (or operating system) specific interrupt handler; for
  * example, a thread context save is performed prior to invoking the interrupt
  * handler.
- * 
+ *
  * The IA-32 code that makes up a "full" interrupt stub is shown below.  A full
  * interrupt stub is one that is associated with an interrupt vector that
  * requires a "beginning of interrupt" (BOI) callout and an "end of interrupt"

drivers/interrupt_controller/loapic_intr.c

@@ -83,7 +83,7 @@
  * should allocate no more than 2 interrupt vectors per priority.  The Pentium4
  * processor expands this support of all acceptance of two interrupts per vector
  * rather than per priority level.
- * 
+ *
  * INCLUDE FILES: loapic.h
  */
 

drivers/pci/pci.c

@@ -70,7 +70,7 @@
  * For each bus it will run through each device on which it will loop on each
  * function and BARs, as long as the criterias does not match or until it hit
  * the limit of bus/dev/functions to scan.
- * 
+ *
  * On a successful match, it will stop the loop, fill in the caller's
  * pci_dev_info structure with the found device information, and return 1.
  * Hopefully, the lookup structure still remembers where it stopped and the

drivers/timer/cortex_m_systick.c

@@ -20,13 +20,13 @@
  * DESCRIPTION
  * This module implements the kernel's CORTEX-M ARM's systick device driver.
  * It provides the standard kernel "system clock driver" interfaces.
- * 
+ *
  * The driver utilizes systick to provide kernel ticks.
- * 
+ *
  * \INTERNAL IMPLEMENTATION DETAILS
  * The systick device provides a 24-bit clear-on-write, decrementing,
  * wrap-on-zero counter. Only edge sensitive triggered interrupt is supported.
- * 
+ *
  * \INTERNAL PACKAGING DETAILS
  * The systick device driver is part of the microkernel in both a monolithic
  * kernel system and a split kernel system; it is not included in the

drivers/timer/hpet.c

@@ -21,9 +21,9 @@
  * This module implements a kernel device driver for the Intel High Precision
  * Event Timer (HPET) device, and provides the standard "system clock driver"
  * interfaces.
- * 
+ *
  * The driver utilizes HPET timer0 to provide kernel ticks.
- * 
+ *
  * \INTERNAL IMPLEMENTATION DETAILS
  * The HPET device driver makes no assumption about the initial state of the
  * HPET, and explicitly puts the device into a reset-like state. It also assumes

include/arch/arm/cortex_m/scs.h

@@ -20,28 +20,28 @@
  * DESCRIPTION
  * Define the System Control Space for the CORTEX-M series of processors and
  * provide an interface for miscellaneous SCS functionalities.
- * 
+ *
  * All register and bit-field names come from the
- * 
+ *
  *   Cortex-M3 Devices
  *   Generic User Guide
  *   ARM DUI 0552A (ID121610)
- * 
+ *
  * and
- * 
+ *
  *   Cortex-M3
  *   Revision r2p1
  *   Technical Reference Manual
  *   ARM DDI 0337I (ID072410)
- * 
+ *
  * documents from ARM.
- * 
+ *
  * The API does not account for all possible usages of the SCS, only the
  * functionalities needed by the kernel. It does not contain NVIC and
  * SCB functionalities either: these can be found in nvic.h and scb.h.
- * 
+ *
  * MPU functionalities are not implemented.
- * 
+ *
  * The same effect can be achieved by directly writing in the registers of the
  * SCS, using the __scs data structure (or hardcoded values), but the APIs found
  * here are less error-prone, especially for registers with multiple instances

include/drivers/pci/pci_mgr.h

@@ -95,7 +95,7 @@ extern "C" {
  * +------------------+------------------+------------------+------------------+
  * |   Device Number  | Function Number  | Register Number  |        00        |
  * +---------------------------------------------------------------------------+
- * 
+ *
  */
 
 union pci_addr_reg {
@@ -580,7 +580,7 @@ union pcie_cap_hdr {
 
 /*
  * MSI Capability register set (32-bit):
- * 
+ *
  * +---------------------------------------------------------------------------+
  * |Register|   Bits 31-24   |   Bits 23-16   |    Bits 15-8   |   Bits 7-0    |
  * +--------+----------------+----------------+----------------+---------------+
@@ -590,9 +590,9 @@ union pcie_cap_hdr {
  * +--------+---------------------------------+--------------------------------+
  * |    0C  |                                 |      Message Data Register     |
  * +---------------------------------------------------------------------------+
- * 
+ *
  * MSI Capability register set (64-bit):
- * 
+ *
  * +---------------------------------------------------------------------------+
  * |Register|   Bits 31-24   |   Bits 23-16   |    Bits 15-8   |   Bits 7-0    |
  * +--------+----------------+----------------+----------------+---------------+

include/misc/ring_buffer.h

@@ -47,7 +47,7 @@ struct ring_buf {
  * will not need to use expensive modulo operations.
  *
  * @param name File-scoped name of the ring buffer to declare
- * @param pow Create a buffer of 2^pow 32-bit elements 
+ * @param pow Create a buffer of 2^pow 32-bit elements
  */
 #define SYS_RING_BUF_DECLARE_POW2(name, pow) \
 	static uint32_t _ring_buffer_data_##name[1 << (pow)]; \

include/net/net_buf.h

@@ -1,6 +1,6 @@
 /** @file
  * @brief Network buffer API
- * 
+ *
  * Network data is passed between application and IP stack via a net_buf struct.
  */
 

include/net/net_ip.h

@@ -1,6 +1,6 @@
 /** @file
  * @brief IPv6 and IPv4 definitions
- * 
+ *
  * Generic IPv6 and IPv4 address definitions.
  */
 

include/net/tinydtls.h

@@ -1,6 +1,6 @@
 /** @file
  * @brief tinyDTLS API
- * 
+ *
  * API providing DTLS functionality.
  */
 

kernel/microkernel/k_memory_pool.c

@@ -332,7 +332,7 @@ static char *get_block_recusive(struct pool_struct *P, int index, int startindex
 		defrag(P,
 		       P->nr_of_frags - 1, /* start from the smallest blocks */
 		       startindex); /* but only until the requested blocksize
-				     * (fragmentation level) !! 
+				     * (fragmentation level) !!
 				     */
 
 		found = search_block_on_frag_level(&(fr_table[index]), &i);

kernel/microkernel/k_pipe_xfer.c

@@ -325,7 +325,7 @@ static int ReaderInProgressIsBlocked(struct _k_pipe_struct *pipe_ptr,
 	    ) {
 		/*
 		 * requester can still wait (for some time or forever), no
-		 * problem for now 
+		 * problem for now
 		 */
 		return 0;
 	}
@@ -835,7 +835,7 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter,
 					continue;
 				} else {
 					/* we could break as well,
-					 * but then nothing else will happen 
+					 * but then nothing else will happen
 					 */
 					return;
 				}
@@ -844,7 +844,7 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter,
 				if (reader_ptr && (_TIME_NB !=
 					_k_pipe_time_type_get(&writer_ptr->args))) {
 					/* force transfer (we make exception
-					 * for non-blocked writer) 
+					 * for non-blocked writer)
 					 */
 					pipe_read_write(pipe_ptr, writer_ptr, reader_ptr);
 					continue;

kernel/nanokernel/include/timeout_q.h

@@ -1,6 +1,6 @@
 /** @file
  * @brief timeout queue for fibers on nanokernel objects
- * 
+ *
  * This file is meant to be included by nanokernel/include/wait_q.h only
  */