checkpatch: error - trailing_whitespace
Change-Id: I819d13f0d7a23e3a61dcda6a3ced18810b192158 Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
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9760129627
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e8563c2f97
16 changed files with 35 additions and 35 deletions
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@ -308,7 +308,7 @@ static int fsl_frdm_k64f_init(struct device *arg)
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/*
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/*
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* install default handler that simply resets the CPU
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* install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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* if configured in the kernel, NOP otherwise
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*/
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*/
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NMI_INIT();
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NMI_INIT();
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@ -47,7 +47,7 @@
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*
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*
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* If the nanokernel has been built without SSE instruction support
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* If the nanokernel has been built without SSE instruction support
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* (CONFIG_SSE), the system treats USE_SSE as if it was USE_FP.
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* (CONFIG_SSE), the system treats USE_SSE as if it was USE_FP.
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*
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*
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* If the nanokernel has been built without floating point resource sharing
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* If the nanokernel has been built without floating point resource sharing
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* support (CONFIG_FP_SHARING), the aforementioned APIs and capabilities do not
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* support (CONFIG_FP_SHARING), the aforementioned APIs and capabilities do not
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* exist.
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* exist.
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@ -60,7 +60,7 @@
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*
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*
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* WARNING
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* WARNING
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* The use of floating point instructions by ISRs is not supported by the
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* The use of floating point instructions by ISRs is not supported by the
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* kernel.
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* kernel.
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*
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*
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* INTERNAL
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* INTERNAL
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* If automatic enabling of floating point resource sharing _is not_ configured
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* If automatic enabling of floating point resource sharing _is not_ configured
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@ -20,22 +20,22 @@
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* DESCRIPTION
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* DESCRIPTION
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* This module provides routines to manage asynchronous interrupts
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* This module provides routines to manage asynchronous interrupts
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* on the IA-32 architecture.
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* on the IA-32 architecture.
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*
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*
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* This module provides the public routine irq_connect(), the private
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* This module provides the public routine irq_connect(), the private
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* routine _IntVecSet(), and the support routines _IntVecAlloc(),
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* routine _IntVecSet(), and the support routines _IntVecAlloc(),
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* _IntVecMarkAllocated() and _IntVecMarkFree().
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* _IntVecMarkAllocated() and _IntVecMarkFree().
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*
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*
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* INTERNAL
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* INTERNAL
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* The _idt_base_address symbol is used to determine the base address of the
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* The _idt_base_address symbol is used to determine the base address of the
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* IDT. (It is generated by the linker script, and doesn't correspond to an
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* IDT. (It is generated by the linker script, and doesn't correspond to an
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* actual global variable.)
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* actual global variable.)
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*
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*
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* Interrupts are handled by an "interrupt stub" whose code is generated by the
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* Interrupts are handled by an "interrupt stub" whose code is generated by the
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* system itself. The stub performs various actions before and after invoking
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* system itself. The stub performs various actions before and after invoking
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* the application (or operating system) specific interrupt handler; for
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* the application (or operating system) specific interrupt handler; for
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* example, a thread context save is performed prior to invoking the interrupt
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* example, a thread context save is performed prior to invoking the interrupt
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* handler.
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* handler.
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*
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*
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* The IA-32 code that makes up a "full" interrupt stub is shown below. A full
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* The IA-32 code that makes up a "full" interrupt stub is shown below. A full
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* interrupt stub is one that is associated with an interrupt vector that
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* interrupt stub is one that is associated with an interrupt vector that
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* requires a "beginning of interrupt" (BOI) callout and an "end of interrupt"
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* requires a "beginning of interrupt" (BOI) callout and an "end of interrupt"
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@ -83,7 +83,7 @@
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* should allocate no more than 2 interrupt vectors per priority. The Pentium4
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* should allocate no more than 2 interrupt vectors per priority. The Pentium4
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* processor expands this support of all acceptance of two interrupts per vector
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* processor expands this support of all acceptance of two interrupts per vector
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* rather than per priority level.
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* rather than per priority level.
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*
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*
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* INCLUDE FILES: loapic.h
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* INCLUDE FILES: loapic.h
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*/
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*/
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@ -70,7 +70,7 @@
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* For each bus it will run through each device on which it will loop on each
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* For each bus it will run through each device on which it will loop on each
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* function and BARs, as long as the criterias does not match or until it hit
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* function and BARs, as long as the criterias does not match or until it hit
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* the limit of bus/dev/functions to scan.
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* the limit of bus/dev/functions to scan.
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*
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*
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* On a successful match, it will stop the loop, fill in the caller's
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* On a successful match, it will stop the loop, fill in the caller's
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* pci_dev_info structure with the found device information, and return 1.
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* pci_dev_info structure with the found device information, and return 1.
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* Hopefully, the lookup structure still remembers where it stopped and the
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* Hopefully, the lookup structure still remembers where it stopped and the
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@ -20,13 +20,13 @@
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* DESCRIPTION
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* DESCRIPTION
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* This module implements the kernel's CORTEX-M ARM's systick device driver.
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* This module implements the kernel's CORTEX-M ARM's systick device driver.
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* It provides the standard kernel "system clock driver" interfaces.
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* It provides the standard kernel "system clock driver" interfaces.
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*
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*
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* The driver utilizes systick to provide kernel ticks.
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* The driver utilizes systick to provide kernel ticks.
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*
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*
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* \INTERNAL IMPLEMENTATION DETAILS
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* \INTERNAL IMPLEMENTATION DETAILS
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* The systick device provides a 24-bit clear-on-write, decrementing,
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* The systick device provides a 24-bit clear-on-write, decrementing,
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* wrap-on-zero counter. Only edge sensitive triggered interrupt is supported.
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* wrap-on-zero counter. Only edge sensitive triggered interrupt is supported.
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*
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*
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* \INTERNAL PACKAGING DETAILS
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* \INTERNAL PACKAGING DETAILS
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* The systick device driver is part of the microkernel in both a monolithic
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* The systick device driver is part of the microkernel in both a monolithic
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* kernel system and a split kernel system; it is not included in the
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* kernel system and a split kernel system; it is not included in the
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@ -21,9 +21,9 @@
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* This module implements a kernel device driver for the Intel High Precision
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* This module implements a kernel device driver for the Intel High Precision
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* Event Timer (HPET) device, and provides the standard "system clock driver"
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* Event Timer (HPET) device, and provides the standard "system clock driver"
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* interfaces.
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* interfaces.
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*
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*
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* The driver utilizes HPET timer0 to provide kernel ticks.
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* The driver utilizes HPET timer0 to provide kernel ticks.
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*
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*
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* \INTERNAL IMPLEMENTATION DETAILS
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* \INTERNAL IMPLEMENTATION DETAILS
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* The HPET device driver makes no assumption about the initial state of the
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* The HPET device driver makes no assumption about the initial state of the
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* HPET, and explicitly puts the device into a reset-like state. It also assumes
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* HPET, and explicitly puts the device into a reset-like state. It also assumes
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@ -20,28 +20,28 @@
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* DESCRIPTION
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* DESCRIPTION
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* Define the System Control Space for the CORTEX-M series of processors and
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* Define the System Control Space for the CORTEX-M series of processors and
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* provide an interface for miscellaneous SCS functionalities.
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* provide an interface for miscellaneous SCS functionalities.
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*
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*
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* All register and bit-field names come from the
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* All register and bit-field names come from the
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*
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*
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* Cortex-M3 Devices
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* Cortex-M3 Devices
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* Generic User Guide
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* Generic User Guide
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* ARM DUI 0552A (ID121610)
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* ARM DUI 0552A (ID121610)
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*
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*
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* and
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* and
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*
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*
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* Cortex-M3
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* Cortex-M3
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* Revision r2p1
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* Revision r2p1
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* Technical Reference Manual
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* Technical Reference Manual
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* ARM DDI 0337I (ID072410)
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* ARM DDI 0337I (ID072410)
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*
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*
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* documents from ARM.
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* documents from ARM.
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*
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*
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* The API does not account for all possible usages of the SCS, only the
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* The API does not account for all possible usages of the SCS, only the
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* functionalities needed by the kernel. It does not contain NVIC and
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* functionalities needed by the kernel. It does not contain NVIC and
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* SCB functionalities either: these can be found in nvic.h and scb.h.
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* SCB functionalities either: these can be found in nvic.h and scb.h.
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*
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*
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* MPU functionalities are not implemented.
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* MPU functionalities are not implemented.
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*
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*
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* The same effect can be achieved by directly writing in the registers of the
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* The same effect can be achieved by directly writing in the registers of the
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* SCS, using the __scs data structure (or hardcoded values), but the APIs found
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* SCS, using the __scs data structure (or hardcoded values), but the APIs found
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* here are less error-prone, especially for registers with multiple instances
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* here are less error-prone, especially for registers with multiple instances
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@ -95,7 +95,7 @@ extern "C" {
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* +------------------+------------------+------------------+------------------+
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* +------------------+------------------+------------------+------------------+
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* | Device Number | Function Number | Register Number | 00 |
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* | Device Number | Function Number | Register Number | 00 |
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* +---------------------------------------------------------------------------+
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* +---------------------------------------------------------------------------+
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*
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*
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*/
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*/
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union pci_addr_reg {
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union pci_addr_reg {
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@ -580,7 +580,7 @@ union pcie_cap_hdr {
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/*
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/*
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* MSI Capability register set (32-bit):
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* MSI Capability register set (32-bit):
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*
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*
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* +---------------------------------------------------------------------------+
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* +---------------------------------------------------------------------------+
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* |Register| Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 |
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* |Register| Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 |
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* +--------+----------------+----------------+----------------+---------------+
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* +--------+----------------+----------------+----------------+---------------+
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@ -590,9 +590,9 @@ union pcie_cap_hdr {
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* +--------+---------------------------------+--------------------------------+
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* +--------+---------------------------------+--------------------------------+
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* | 0C | | Message Data Register |
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* | 0C | | Message Data Register |
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* +---------------------------------------------------------------------------+
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* +---------------------------------------------------------------------------+
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*
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*
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* MSI Capability register set (64-bit):
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* MSI Capability register set (64-bit):
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*
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*
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* +---------------------------------------------------------------------------+
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* +---------------------------------------------------------------------------+
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* |Register| Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 |
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* |Register| Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 |
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* +--------+----------------+----------------+----------------+---------------+
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* +--------+----------------+----------------+----------------+---------------+
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@ -47,7 +47,7 @@ struct ring_buf {
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* will not need to use expensive modulo operations.
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* will not need to use expensive modulo operations.
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*
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*
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* @param name File-scoped name of the ring buffer to declare
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* @param name File-scoped name of the ring buffer to declare
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* @param pow Create a buffer of 2^pow 32-bit elements
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* @param pow Create a buffer of 2^pow 32-bit elements
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*/
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*/
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#define SYS_RING_BUF_DECLARE_POW2(name, pow) \
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#define SYS_RING_BUF_DECLARE_POW2(name, pow) \
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static uint32_t _ring_buffer_data_##name[1 << (pow)]; \
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static uint32_t _ring_buffer_data_##name[1 << (pow)]; \
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@ -1,6 +1,6 @@
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/** @file
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/** @file
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* @brief Network buffer API
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* @brief Network buffer API
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*
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*
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* Network data is passed between application and IP stack via a net_buf struct.
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* Network data is passed between application and IP stack via a net_buf struct.
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*/
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*/
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/** @file
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/** @file
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* @brief IPv6 and IPv4 definitions
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* @brief IPv6 and IPv4 definitions
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*
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*
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* Generic IPv6 and IPv4 address definitions.
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* Generic IPv6 and IPv4 address definitions.
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*/
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*/
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@ -1,6 +1,6 @@
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/** @file
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/** @file
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* @brief tinyDTLS API
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* @brief tinyDTLS API
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*
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*
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* API providing DTLS functionality.
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* API providing DTLS functionality.
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*/
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*/
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@ -332,7 +332,7 @@ static char *get_block_recusive(struct pool_struct *P, int index, int startindex
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defrag(P,
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defrag(P,
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P->nr_of_frags - 1, /* start from the smallest blocks */
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P->nr_of_frags - 1, /* start from the smallest blocks */
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startindex); /* but only until the requested blocksize
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startindex); /* but only until the requested blocksize
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* (fragmentation level) !!
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* (fragmentation level) !!
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*/
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*/
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found = search_block_on_frag_level(&(fr_table[index]), &i);
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found = search_block_on_frag_level(&(fr_table[index]), &i);
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@ -325,7 +325,7 @@ static int ReaderInProgressIsBlocked(struct _k_pipe_struct *pipe_ptr,
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) {
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) {
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/*
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/*
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* requester can still wait (for some time or forever), no
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* requester can still wait (for some time or forever), no
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* problem for now
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* problem for now
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*/
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*/
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return 0;
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return 0;
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}
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}
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continue;
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continue;
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} else {
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} else {
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/* we could break as well,
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/* we could break as well,
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* but then nothing else will happen
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* but then nothing else will happen
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*/
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*/
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return;
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return;
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}
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}
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if (reader_ptr && (_TIME_NB !=
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if (reader_ptr && (_TIME_NB !=
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_k_pipe_time_type_get(&writer_ptr->args))) {
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_k_pipe_time_type_get(&writer_ptr->args))) {
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/* force transfer (we make exception
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/* force transfer (we make exception
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* for non-blocked writer)
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* for non-blocked writer)
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*/
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*/
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pipe_read_write(pipe_ptr, writer_ptr, reader_ptr);
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pipe_read_write(pipe_ptr, writer_ptr, reader_ptr);
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continue;
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continue;
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/** @file
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/** @file
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* @brief timeout queue for fibers on nanokernel objects
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* @brief timeout queue for fibers on nanokernel objects
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*
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*
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* This file is meant to be included by nanokernel/include/wait_q.h only
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* This file is meant to be included by nanokernel/include/wait_q.h only
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*/
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*/
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