From e6dfae0fea0153ef6f8f943c23e30b436660f40e Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Thu, 15 Oct 2020 08:10:12 -0400 Subject: [PATCH] soc/intel_adsp: Fix linker warning The linker will emit a warning condition when a section with a declared alignment doesn't naturally start on that alignment (which begets the question of why the declared alignment syntax exists at all...). Do the alignment for .bss between the sections instead as a simple workaround. Note that this alignment isn't architecturally required, as current Zephyr targets don't use the page-aligned pseudo-MMU on this hardware; the only requirement is alignment to the 64 byte cache stride. It should work to pack .bss tightly. But when I try that, I get an error from the rimage tool, which is apparently unprepared for non-4k-aligned sections? Signed-off-by: Andy Ross Signed-off-by: Anas Nashif --- soc/xtensa/intel_adsp/cavs_v15/linker.ld | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld index 9feb781db31..08c9d08b7f9 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld @@ -465,9 +465,10 @@ SECTIONS *(.cached .cached.*) } >ram :ram_phdr - .bss SEGSTART_UNCACHED (NOLOAD) : ALIGN(4096) + . = ALIGN(4096); + + .bss SEGSTART_UNCACHED (NOLOAD) : { - . = ALIGN(4096); _bss_start = ABSOLUTE(.); *(.dynsbss) *(.sbss)