diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 2ba4587c9ca..5e3049433a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -16,9 +16,13 @@ config FLOAT_HARD help This option enables the hard-float calling convention. +choice RISCV_GP_PURPOSE + prompt "Purpose of the global pointer (GP) register" + default RISCV_GP if RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING + config RISCV_GP bool "RISC-V global pointer relative addressing" - default n + depends on RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING help Use global pointer relative addressing for small globals declared anywhere in the executable. It can benefit performance and reduce @@ -30,7 +34,6 @@ config RISCV_GP config RISCV_CURRENT_VIA_GP bool "Store current thread into the global pointer (GP) register" - depends on !RISCV_GP depends on MP_MAX_NUM_CPUS > 1 select ARCH_HAS_CUSTOM_CURRENT_IMPL help @@ -38,6 +41,8 @@ config RISCV_CURRENT_VIA_GP When is enabled, calls to `arch_current_thread()` & `k_sched_current_thread_query()` will be reduced to a single register read. +endchoice # RISCV_GP_PURPOSE + config RISCV_ALWAYS_SWITCH_THROUGH_ECALL bool "Do not use mret outside a trap handler context" depends on MULTITHREADING @@ -148,6 +153,12 @@ config RISCV_SOC_HAS_CUSTOM_SYS_IO the RISC-V SoC needs to do something different and more than reading and writing the registers. +config RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING + bool + help + Selected when SoC has implemented the initialization of global pointer (GP) + at program start, or earlier than any instruction using GP relative addressing. + config RISCV_SOC_CONTEXT_SAVE bool "SOC-based context saving in IRQ handlers" select RISCV_SOC_OFFSETS diff --git a/soc/andestech/ae350/Kconfig b/soc/andestech/ae350/Kconfig index d82c22e3819..bcd2aa5329f 100644 --- a/soc/andestech/ae350/Kconfig +++ b/soc/andestech/ae350/Kconfig @@ -5,6 +5,7 @@ config SOC_SERIES_ANDES_AE350 select RISCV select RISCV_PRIVILEGED select RISCV_HAS_PLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING imply XIP config SOC_ANDES_AE350 diff --git a/soc/andestech/ae350/Kconfig.defconfig b/soc/andestech/ae350/Kconfig.defconfig index 49d6af78c91..b0a2c6b9afa 100644 --- a/soc/andestech/ae350/Kconfig.defconfig +++ b/soc/andestech/ae350/Kconfig.defconfig @@ -21,9 +21,6 @@ config RISCV_GENERIC_TOOLCHAIN config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 2ND_LVL_ISR_TBL_OFFSET default 12 diff --git a/soc/espressif/esp32c2/Kconfig b/soc/espressif/esp32c2/Kconfig index cc98488000c..a0e6c98e31a 100644 --- a/soc/espressif/esp32c2/Kconfig +++ b/soc/espressif/esp32c2/Kconfig @@ -3,7 +3,7 @@ config SOC_SERIES_ESP32C2 select RISCV - select RISCV_GP + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select DYNAMIC_INTERRUPTS select CLOCK_CONTROL select PINCTRL diff --git a/soc/espressif/esp32c3/Kconfig b/soc/espressif/esp32c3/Kconfig index c3a562d0f98..571a7ba1dd8 100644 --- a/soc/espressif/esp32c3/Kconfig +++ b/soc/espressif/esp32c3/Kconfig @@ -3,7 +3,7 @@ config SOC_SERIES_ESP32C3 select RISCV - select RISCV_GP + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select DYNAMIC_INTERRUPTS select CLOCK_CONTROL select PINCTRL diff --git a/soc/espressif/esp32c6/Kconfig b/soc/espressif/esp32c6/Kconfig index 88963c36cd8..3908eb4ee1e 100644 --- a/soc/espressif/esp32c6/Kconfig +++ b/soc/espressif/esp32c6/Kconfig @@ -3,7 +3,7 @@ config SOC_SERIES_ESP32C6 select RISCV - select RISCV_GP + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select DYNAMIC_INTERRUPTS select CLOCK_CONTROL select PINCTRL diff --git a/soc/gd/gd32/gd32vf103/Kconfig b/soc/gd/gd32/gd32vf103/Kconfig index 4ec9057d196..b14bddbd46a 100644 --- a/soc/gd/gd32/gd32vf103/Kconfig +++ b/soc/gd/gd32/gd32vf103/Kconfig @@ -13,6 +13,7 @@ config SOC_SERIES_GD32VF103 select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI select RISCV_HAS_CLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select ATOMIC_OPERATIONS_C select INCLUDE_RESET_VECTOR select GD32_HAS_AFIO_PINMUX diff --git a/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 index e980d818e95..e8c3d949e65 100644 --- a/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 +++ b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 @@ -17,9 +17,6 @@ config RISCV_MCAUSE_EXCEPTION_MASK config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config NUM_IRQS default 87 if NUCLEI_ECLIC default 16 if !NUCLEI_ECLIC diff --git a/soc/intel/intel_niosv/niosv/Kconfig b/soc/intel/intel_niosv/niosv/Kconfig index 8e21016f9de..72e38341ea0 100644 --- a/soc/intel/intel_niosv/niosv/Kconfig +++ b/soc/intel/intel_niosv/niosv/Kconfig @@ -11,6 +11,7 @@ config SOC_SERIES_NIOSV select RISCV_ISA_EXT_A select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING imply XIP config SOC_NIOSV_M diff --git a/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series b/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series index 4d859d24e4e..69eac87f7ec 100644 --- a/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series +++ b/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series @@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config NUM_IRQS # Platform interrupts IRQs index start from index 16 default 32 -config RISCV_GP - default y - config RISCV_SOC_INTERRUPT_INIT default y diff --git a/soc/ite/ec/it8xxx2/Kconfig b/soc/ite/ec/it8xxx2/Kconfig index a7cf5b732f5..739278e97f9 100644 --- a/soc/ite/ec/it8xxx2/Kconfig +++ b/soc/ite/ec/it8xxx2/Kconfig @@ -6,6 +6,7 @@ config SOC_SERIES_IT8XXX2 select HAS_PM select ARCH_HAS_CUSTOM_CPU_IDLE select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING if SOC_SERIES_IT8XXX2 diff --git a/soc/ite/ec/it8xxx2/Kconfig.defconfig.series b/soc/ite/ec/it8xxx2/Kconfig.defconfig.series index 22140af14df..26e961d2dcc 100644 --- a/soc/ite/ec/it8xxx2/Kconfig.defconfig.series +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.series @@ -3,9 +3,6 @@ if SOC_SERIES_IT8XXX2 -config RISCV_GP - default y - config ARCH_HAS_CUSTOM_BUSY_WAIT default y diff --git a/soc/lowrisc/opentitan/Kconfig b/soc/lowrisc/opentitan/Kconfig index 36662709cce..c76751f6e96 100644 --- a/soc/lowrisc/opentitan/Kconfig +++ b/soc/lowrisc/opentitan/Kconfig @@ -16,6 +16,7 @@ config SOC_OPENTITAN select RISCV select RISCV_PRIVILEGED select RISCV_HAS_PLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING # OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode. select RISCV_VECTORED_MODE select GEN_IRQ_VECTOR_TABLE diff --git a/soc/lowrisc/opentitan/Kconfig.defconfig b/soc/lowrisc/opentitan/Kconfig.defconfig index b77a9405fbe..7cbedf1f60b 100644 --- a/soc/lowrisc/opentitan/Kconfig.defconfig +++ b/soc/lowrisc/opentitan/Kconfig.defconfig @@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 2ND_LVL_ISR_TBL_OFFSET default 32 diff --git a/soc/microchip/miv/miv/Kconfig b/soc/microchip/miv/miv/Kconfig index 58e04c05a35..2dbbd102b04 100644 --- a/soc/microchip/miv/miv/Kconfig +++ b/soc/microchip/miv/miv/Kconfig @@ -7,6 +7,7 @@ config SOC_SERIES_MIV select RISCV select RISCV_PRIVILEGED select RISCV_HAS_PLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING imply XIP config SOC_MIV diff --git a/soc/microchip/miv/miv/Kconfig.defconfig b/soc/microchip/miv/miv/Kconfig.defconfig index 4e2653f5cd0..d329bf0b085 100644 --- a/soc/microchip/miv/miv/Kconfig.defconfig +++ b/soc/microchip/miv/miv/Kconfig.defconfig @@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 2ND_LVL_ISR_TBL_OFFSET default 12 diff --git a/soc/microchip/miv/polarfire/Kconfig b/soc/microchip/miv/polarfire/Kconfig index a39e34de744..d214e6e7239 100644 --- a/soc/microchip/miv/polarfire/Kconfig +++ b/soc/microchip/miv/polarfire/Kconfig @@ -7,13 +7,14 @@ config SOC_SERIES_POLARFIRE select RISCV select RISCV_PRIVILEGED select RISCV_HAS_PLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING imply XIP config SOC_POLARFIRE select 64BIT select SCHED_IPI_SUPPORTED select ATOMIC_OPERATIONS_BUILTIN - select RISCV_GP + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select USE_SWITCH_SUPPORTED select USE_SWITCH diff --git a/soc/microchip/miv/polarfire/Kconfig.defconfig b/soc/microchip/miv/polarfire/Kconfig.defconfig index a694c9a50b2..26b0f2c9a25 100644 --- a/soc/microchip/miv/polarfire/Kconfig.defconfig +++ b/soc/microchip/miv/polarfire/Kconfig.defconfig @@ -13,9 +13,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 2ND_LVL_ISR_TBL_OFFSET default 13 diff --git a/soc/neorv32/Kconfig b/soc/neorv32/Kconfig index c4725545b28..d0b2a04967b 100644 --- a/soc/neorv32/Kconfig +++ b/soc/neorv32/Kconfig @@ -9,6 +9,7 @@ config SOC_NEORV32 select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI select RISCV_PRIVILEGED + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING imply XIP if SOC_NEORV32 diff --git a/soc/neorv32/Kconfig.defconfig b/soc/neorv32/Kconfig.defconfig index 67d458f7398..3608ae244a0 100644 --- a/soc/neorv32/Kconfig.defconfig +++ b/soc/neorv32/Kconfig.defconfig @@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config NUM_IRQS default 32 -config RISCV_GP - default y - config SYSCON default y diff --git a/soc/qemu/virt_riscv/Kconfig b/soc/qemu/virt_riscv/Kconfig index 0145f14b854..84a26dbe4a9 100644 --- a/soc/qemu/virt_riscv/Kconfig +++ b/soc/qemu/virt_riscv/Kconfig @@ -10,6 +10,7 @@ config SOC_FAMILY_QEMU_VIRT_RISCV select RISCV select RISCV_PRIVILEGED select RISCV_HAS_PLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING imply XIP if SOC_FAMILY_QEMU_VIRT_RISCV diff --git a/soc/qemu/virt_riscv/Kconfig.defconfig b/soc/qemu/virt_riscv/Kconfig.defconfig index f5e99f5edc8..599c62a1acd 100644 --- a/soc/qemu/virt_riscv/Kconfig.defconfig +++ b/soc/qemu/virt_riscv/Kconfig.defconfig @@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 2ND_LVL_ISR_TBL_OFFSET default 12 diff --git a/soc/renode/riscv_virtual/Kconfig b/soc/renode/riscv_virtual/Kconfig index 8fb2a2f7238..2cd9cfe0249 100644 --- a/soc/renode/riscv_virtual/Kconfig +++ b/soc/renode/riscv_virtual/Kconfig @@ -13,4 +13,5 @@ config SOC_RISCV_VIRTUAL_RENODE select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI select RISCV_HAS_PLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING imply XIP diff --git a/soc/renode/riscv_virtual/Kconfig.defconfig b/soc/renode/riscv_virtual/Kconfig.defconfig index 8b00c5867ab..bf7a6ae4e92 100644 --- a/soc/renode/riscv_virtual/Kconfig.defconfig +++ b/soc/renode/riscv_virtual/Kconfig.defconfig @@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 1ST_LEVEL_INTERRUPT_BITS default 4 diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig b/soc/sifive/sifive_freedom/fe300/Kconfig index c8004564cab..9743319a3c1 100644 --- a/soc/sifive/sifive_freedom/fe300/Kconfig +++ b/soc/sifive/sifive_freedom/fe300/Kconfig @@ -10,6 +10,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FE300 select RISCV_PRIVILEGED select RISCV_HAS_PLIC select RISCV_PMP + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select RISCV_ISA_RV32I select RISCV_ISA_EXT_M diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig b/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig index c280c62ef43..62c7249a73c 100644 --- a/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig +++ b/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig @@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 2ND_LVL_ISR_TBL_OFFSET default 12 diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig b/soc/sifive/sifive_freedom/fu500/Kconfig index fb54b7451bb..5e1b5539d0a 100644 --- a/soc/sifive/sifive_freedom/fu500/Kconfig +++ b/soc/sifive/sifive_freedom/fu500/Kconfig @@ -12,6 +12,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU500 select RISCV_PRIVILEGED select RISCV_HAS_PLIC select RISCV_PMP + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select RISCV_ISA_RV64I select RISCV_ISA_EXT_M diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig b/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig index e7aafaae73b..b5fcb319328 100644 --- a/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig +++ b/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig @@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 2ND_LVL_ISR_TBL_OFFSET default 12 diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig b/soc/sifive/sifive_freedom/fu700/Kconfig index 5644ea390ab..fddd64d37ad 100644 --- a/soc/sifive/sifive_freedom/fu700/Kconfig +++ b/soc/sifive/sifive_freedom/fu700/Kconfig @@ -11,6 +11,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU700 select RISCV_PRIVILEGED select RISCV_HAS_PLIC select RISCV_PMP + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select RISCV_ISA_RV64I select RISCV_ISA_EXT_M diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig b/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig index c990500fcf3..077ed7dad1c 100644 --- a/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig +++ b/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig @@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 2ND_LVL_ISR_TBL_OFFSET default 12 diff --git a/soc/snps/nsim/arc_v/rmx/Kconfig b/soc/snps/nsim/arc_v/rmx/Kconfig index 2e0ae394c78..3781cd7fd72 100644 --- a/soc/snps/nsim/arc_v/rmx/Kconfig +++ b/soc/snps/nsim/arc_v/rmx/Kconfig @@ -12,6 +12,7 @@ config SOC_SERIES_RMX select RISCV_ISA_EXT_C select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select INCLUDE_RESET_VECTOR select ATOMIC_OPERATIONS_BUILTIN imply XIP diff --git a/soc/snps/nsim/arc_v/rmx/Kconfig.defconfig b/soc/snps/nsim/arc_v/rmx/Kconfig.defconfig index 725b12f9b5e..8693acdbe96 100644 --- a/soc/snps/nsim/arc_v/rmx/Kconfig.defconfig +++ b/soc/snps/nsim/arc_v/rmx/Kconfig.defconfig @@ -6,9 +6,6 @@ if SOC_SERIES_RMX config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config MULTI_LEVEL_INTERRUPTS default n diff --git a/soc/starfive/jh71xx/Kconfig b/soc/starfive/jh71xx/Kconfig index 7d04259343a..f8bfdf2c92e 100644 --- a/soc/starfive/jh71xx/Kconfig +++ b/soc/starfive/jh71xx/Kconfig @@ -5,6 +5,7 @@ config SOC_SERIES_STARFIVE_JH71XX select RISCV select RISCV_PRIVILEGED select RISCV_HAS_PLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING imply XIP config SOC_JH7100 diff --git a/soc/starfive/jh71xx/Kconfig.defconfig b/soc/starfive/jh71xx/Kconfig.defconfig index c20bde5ee58..103d4ebcbad 100644 --- a/soc/starfive/jh71xx/Kconfig.defconfig +++ b/soc/starfive/jh71xx/Kconfig.defconfig @@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config 2ND_LVL_ISR_TBL_OFFSET default 12 diff --git a/soc/telink/tlsr/tlsr951x/Kconfig b/soc/telink/tlsr/tlsr951x/Kconfig index 5b2b6f59627..a629b21c3d3 100644 --- a/soc/telink/tlsr/tlsr951x/Kconfig +++ b/soc/telink/tlsr/tlsr951x/Kconfig @@ -12,6 +12,7 @@ config SOC_SERIES_TLSR951X select RISCV_ISA_EXT_ZIFENCEI select RISCV_PRIVILEGED select RISCV_HAS_PLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING select HAS_TELINK_DRIVERS select ATOMIC_OPERATIONS_BUILTIN select CPU_HAS_FPU diff --git a/soc/telink/tlsr/tlsr951x/Kconfig.defconfig b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig index 6cd3c6a26b8..b210321b079 100644 --- a/soc/telink/tlsr/tlsr951x/Kconfig.defconfig +++ b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig @@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_GP - default y - config NUM_IRQS default 64 diff --git a/tests/arch/riscv/userspace/riscv_gp/testcase.yaml b/tests/arch/riscv/userspace/riscv_gp/testcase.yaml index cedec864a2e..8d4a08a4ddf 100644 --- a/tests/arch/riscv/userspace/riscv_gp/testcase.yaml +++ b/tests/arch/riscv/userspace/riscv_gp/testcase.yaml @@ -8,8 +8,6 @@ tests: arch.riscv64.riscv_gp.relative_addressing: extra_configs: - CONFIG_RISCV_GP=y - - CONFIG_RISCV_CURRENT_VIA_GP=n arch.riscv64.riscv_gp.thread_pointer: extra_configs: - CONFIG_RISCV_CURRENT_VIA_GP=y - - CONFIG_RISCV_GP=n