arch: arm: aarch64: linker.ld: Clean-up
This commit cleans-up the linker.ld file for the AArch64 arch. * Convert all TAB characters to SPACE. * Fix insane placement of curly brackets. * Fix overall text alignments. * Remove the special handlings for the Cortex-M devices that were copied from `include/arm/aarch32/cortex_m/scripts/linker.ld`. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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1 changed files with 158 additions and 172 deletions
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@ -34,15 +34,15 @@
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#endif
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#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)
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#define ROM_ADDR RAM_ADDR
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#define ROM_ADDR RAM_ADDR
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#else
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#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
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#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
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#endif
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#if CONFIG_FLASH_LOAD_SIZE > 0
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#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE
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#else
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#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)
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#define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)
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#endif
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#if defined(CONFIG_XIP)
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@ -63,23 +63,23 @@
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* to make linker section alignment comply with MPU granularity.
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*/
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#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
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_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
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_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
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#else
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/* If building without MPU support, use default 4-byte alignment. */
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_region_min_align = 4;
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/* If building without MPU support, use default 4-byte alignment. */
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_region_min_align = 4;
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#endif
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#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
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#define MPU_ALIGN(region_size) \
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#define MPU_ALIGN(region_size) \
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. = ALIGN(_region_min_align); \
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. = ALIGN( 1 << LOG2CEIL(region_size))
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#else
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#define MPU_ALIGN(region_size) \
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#define MPU_ALIGN(region_size) \
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. = ALIGN(_region_min_align)
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#endif
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MEMORY
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{
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{
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FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
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#ifdef DT_CCM_BASE_ADDRESS
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CCM (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K
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@ -87,12 +87,12 @@ MEMORY
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SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
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/* Used by and documented in include/linker/intlist.ld */
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IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K
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}
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}
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ENTRY(CONFIG_KERNEL_ENTRY)
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SECTIONS
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{
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{
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#include <linker/rel-sections.ld>
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@ -388,50 +388,36 @@ SECTIONS
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/DISCARD/ : { *(.note.GNU-stack) }
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#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)
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#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0
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#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)
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#elif defined(CONFIG_CPU_HAS_NRF_IDAU)
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/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. */
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#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))
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#else
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#define NSC_ALIGN . = ALIGN(4)
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#endif
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#ifdef CONFIG_CPU_HAS_NRF_IDAU
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#define NSC_ALIGN_END . = ALIGN(0x8000)
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#else
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#define NSC_ALIGN_END . = ALIGN(4)
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#endif
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SECTION_PROLOGUE(.gnu.sgstubs,,)
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{
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SECTION_PROLOGUE(.gnu.sgstubs,,)
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{
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NSC_ALIGN;
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__sg_start = .;
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/* No input section necessary, since the Secure Entry Veneers are
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automatically placed after the .gnu.sgstubs output section. */
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} GROUP_LINK_IN(ROMABLE_REGION)
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__sg_end = .;
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__sg_size = __sg_end - __sg_start;
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NSC_ALIGN_END;
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__nsc_size = . - __sg_start;
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} GROUP_LINK_IN(ROMABLE_REGION)
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__sg_end = .;
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__sg_size = __sg_end - __sg_start;
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NSC_ALIGN_END;
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__nsc_size = . - __sg_start;
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#ifdef CONFIG_CPU_HAS_NRF_IDAU
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ASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))
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== (0x8000 - (__sg_start % 0x8000))
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&& (0x8000 - (__sg_start % 0x8000)) >= 32
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&& (0x8000 - (__sg_start % 0x8000)) <= 4096,
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"The Non-Secure Callable region size must be a power of 2 \
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between 32 and 4096 bytes.")
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#endif
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#endif /* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS */
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/* Must be last in romable region */
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SECTION_PROLOGUE(.last_section,(NOLOAD),)
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{
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} GROUP_LINK_IN(ROMABLE_REGION)
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/* Must be last in romable region */
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SECTION_PROLOGUE(.last_section,(NOLOAD),)
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{
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} GROUP_LINK_IN(ROMABLE_REGION)
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/* To provide the image size as a const expression,
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/* To provide the image size as a const expression,
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* calculate this value here. */
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_flash_used = LOADADDR(.last_section) - _image_rom_start;
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_flash_used = LOADADDR(.last_section) - _image_rom_start;
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}
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}
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