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arch: arm: aarch64: linker.ld: Clean-up

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This commit cleans-up the linker.ld file for the AArch64 arch.

* Convert all TAB characters to SPACE.
* Fix insane placement of curly brackets.
* Fix overall text alignments.
* Remove the special handlings for the Cortex-M devices that were
  copied from `include/arm/aarch32/cortex_m/scripts/linker.ld`.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2020-02-10 15:02:53 +09:00 • committed by Ioannis Glaropoulos
commit e619e36b1b
1 changed files with 158 additions and 172 deletions
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66
include/arch/arm/aarch64/scripts/linker.ld
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@ -34,15 +34,15 @@
#endif #endif
#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0) #if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)
#define ROM_ADDR RAM_ADDR #define ROM_ADDR RAM_ADDR
#else #else
#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET) #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
#endif #endif
#if CONFIG_FLASH_LOAD_SIZE > 0 #if CONFIG_FLASH_LOAD_SIZE > 0
#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE
#else #else
#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET) #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)
#endif #endif
#if defined(CONFIG_XIP) #if defined(CONFIG_XIP)
@ -63,23 +63,23 @@
* to make linker section alignment comply with MPU granularity. * to make linker section alignment comply with MPU granularity.
*/ */
#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE) #if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE; _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
#else #else
/* If building without MPU support, use default 4-byte alignment. */ /* If building without MPU support, use default 4-byte alignment. */
_region_min_align = 4; _region_min_align = 4;
#endif #endif
#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT) #if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
#define MPU_ALIGN(region_size) \ #define MPU_ALIGN(region_size) \
. = ALIGN(_region_min_align); \ . = ALIGN(_region_min_align); \
. = ALIGN( 1 << LOG2CEIL(region_size)) . = ALIGN( 1 << LOG2CEIL(region_size))
#else #else
#define MPU_ALIGN(region_size) \ #define MPU_ALIGN(region_size) \
. = ALIGN(_region_min_align) . = ALIGN(_region_min_align)
#endif #endif
MEMORY MEMORY
{ {
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
#ifdef DT_CCM_BASE_ADDRESS #ifdef DT_CCM_BASE_ADDRESS
CCM (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K CCM (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K
@ -87,12 +87,12 @@ MEMORY
SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
/* Used by and documented in include/linker/intlist.ld */ /* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K
} }
ENTRY(CONFIG_KERNEL_ENTRY) ENTRY(CONFIG_KERNEL_ENTRY)
SECTIONS SECTIONS
{ {
#include <linker/rel-sections.ld> #include <linker/rel-sections.ld>
@ -388,50 +388,36 @@ SECTIONS
/DISCARD/ : { *(.note.GNU-stack) } /DISCARD/ : { *(.note.GNU-stack) }
#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS) #if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)
#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 #if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0
#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS) #define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)
#elif defined(CONFIG_CPU_HAS_NRF_IDAU)
/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. */
#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))
#else #else
#define NSC_ALIGN . = ALIGN(4) #define NSC_ALIGN . = ALIGN(4)
#endif #endif
#ifdef CONFIG_CPU_HAS_NRF_IDAU
#define NSC_ALIGN_END . = ALIGN(0x8000)
#else
#define NSC_ALIGN_END . = ALIGN(4) #define NSC_ALIGN_END . = ALIGN(4)
#endif
SECTION_PROLOGUE(.gnu.sgstubs,,) SECTION_PROLOGUE(.gnu.sgstubs,,)
{ {
NSC_ALIGN; NSC_ALIGN;
__sg_start = .; __sg_start = .;
/* No input section necessary, since the Secure Entry Veneers are /* No input section necessary, since the Secure Entry Veneers are
automatically placed after the .gnu.sgstubs output section. */ automatically placed after the .gnu.sgstubs output section. */
} GROUP_LINK_IN(ROMABLE_REGION) } GROUP_LINK_IN(ROMABLE_REGION)
__sg_end = .; __sg_end = .;
__sg_size = __sg_end - __sg_start; __sg_size = __sg_end - __sg_start;
NSC_ALIGN_END; NSC_ALIGN_END;
__nsc_size = . - __sg_start; __nsc_size = . - __sg_start;
#ifdef CONFIG_CPU_HAS_NRF_IDAU
ASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))
== (0x8000 - (__sg_start % 0x8000))
&& (0x8000 - (__sg_start % 0x8000)) >= 32
&& (0x8000 - (__sg_start % 0x8000)) <= 4096,
"The Non-Secure Callable region size must be a power of 2 \
between 32 and 4096 bytes.")
#endif
#endif /* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS */ #endif /* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS */
/* Must be last in romable region */ /* Must be last in romable region */
SECTION_PROLOGUE(.last_section,(NOLOAD),) SECTION_PROLOGUE(.last_section,(NOLOAD),)
{ {
} GROUP_LINK_IN(ROMABLE_REGION) } GROUP_LINK_IN(ROMABLE_REGION)
/* To provide the image size as a const expression, /* To provide the image size as a const expression,
* calculate this value here. */ * calculate this value here. */
_flash_used = LOADADDR(.last_section) - _image_rom_start; _flash_used = LOADADDR(.last_section) - _image_rom_start;
} }