diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola.dts b/boards/xtensa/esp32s2_saola/esp32s2_saola.dts
index f5dc69c5afc..9983385aad9 100644
--- a/boards/xtensa/esp32s2_saola/esp32s2_saola.dts
+++ b/boards/xtensa/esp32s2_saola/esp32s2_saola.dts
@@ -19,6 +19,10 @@
 	};
 };
 
+&cpu0 {
+	clock-frequency = <ESP32_CLK_CPU_240M>;
+};
+
 &uart0 {
 	status = "okay";
 	current-speed = <115200>;
diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig
index f841cd5ff57..fc0ccd76f84 100644
--- a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig
+++ b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig
@@ -24,4 +24,6 @@ CONFIG_GPIO_ESP32=y
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n
 
+CONFIG_CLOCK_CONTROL=y
+
 CONFIG_BOOTLOADER_ESP_IDF=y
diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt
index c9d2724f653..0e543a914e6 100644
--- a/drivers/clock_control/CMakeLists.txt
+++ b/drivers/clock_control/CMakeLists.txt
@@ -4,6 +4,7 @@ zephyr_library()
 
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE              beetle_clock_control.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32               clock_control_esp32.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32S2             clock_control_esp32s2.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX               clock_control_litex.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X            clock_control_lpc11u6x.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC            clock_control_mchp_xec.c)
diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig
index 5a604cc54a1..cf829f0cade 100644
--- a/drivers/clock_control/Kconfig
+++ b/drivers/clock_control/Kconfig
@@ -48,6 +48,8 @@ source "drivers/clock_control/Kconfig.rv32m1"
 
 source "drivers/clock_control/Kconfig.esp32"
 
+source "drivers/clock_control/Kconfig.esp32s2"
+
 source "drivers/clock_control/Kconfig.litex"
 
 source "drivers/clock_control/Kconfig.rcar"
diff --git a/drivers/clock_control/Kconfig.esp32s2 b/drivers/clock_control/Kconfig.esp32s2
new file mode 100644
index 00000000000..50821cfd1e0
--- /dev/null
+++ b/drivers/clock_control/Kconfig.esp32s2
@@ -0,0 +1,10 @@
+# ESP32S2 Clock Driver configuration options
+
+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_ESP32S2
+	bool "ESP32S2 Clock driver"
+	depends on SOC_ESP32S2
+	help
+	  Enable support for ESP32S2 clock driver.
diff --git a/drivers/clock_control/clock_control_esp32s2.c b/drivers/clock_control/clock_control_esp32s2.c
new file mode 100644
index 00000000000..d61e674cccd
--- /dev/null
+++ b/drivers/clock_control/clock_control_esp32s2.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT espressif_esp32_rtc
+
+#include <dt-bindings/clock/esp32s2_clock.h>
+#include <soc/rtc.h>
+#include <soc/apb_ctrl_reg.h>
+#include <soc/timer_group_reg.h>
+#include <regi2c_ctrl.h>
+#include <hal/clk_gate_ll.h>
+#include <rtc_clk_common.h>
+
+#include <soc.h>
+#include <drivers/clock_control.h>
+#include <driver/periph_ctrl.h>
+
+struct esp32_clock_config {
+	uint32_t clk_src_sel;
+	uint32_t cpu_freq;
+	uint32_t xtal_freq_sel;
+	uint32_t xtal_div;
+};
+
+#define DEV_CFG(dev)                ((struct esp32_clock_config *)(dev->config))
+
+/*
+ * Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
+ * On the ESP32-S2, 480MHz PLL is enabled at reset.
+ */
+static uint32_t s_cur_pll_freq = 480U;
+
+/* function prototypes */
+extern void rtc_clk_cpu_freq_to_xtal(int freq, int div);
+extern void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq);
+
+static void esp_clk_cpu_freq_to_8m(void)
+{
+	ets_update_cpu_frequency(8);
+	REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
+	REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0);
+	REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M);
+	rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
+}
+
+static void esp_clk_bbpll_disable(void)
+{
+	SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD |
+			RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
+
+	s_cur_pll_freq = 0;
+}
+
+static void esp_clk_bbpll_enable(void)
+{
+	CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD |
+				RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
+}
+
+void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
+{
+	/* Update scale factors used by ets_delay_us */
+	esp_rom_g_ticks_per_us_pro = ticks_per_us;
+}
+
+static int esp_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
+{
+	int dbias = DIG_DBIAS_80M_160M;
+	int per_conf = DPORT_CPUPERIOD_SEL_80;
+
+	if (cpu_freq_mhz == 80) {
+		/* nothing to do */
+	} else if (cpu_freq_mhz == 160) {
+		per_conf = DPORT_CPUPERIOD_SEL_160;
+	} else if (cpu_freq_mhz == 240) {
+		dbias = DIG_DBIAS_240M;
+		per_conf = DPORT_CPUPERIOD_SEL_240;
+	} else {
+		return -EINVAL;
+	}
+	REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, per_conf);
+	REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0);
+	REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
+	REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
+	rtc_clk_apb_freq_update(MHZ(80));
+	ets_update_cpu_frequency(cpu_freq_mhz);
+
+	return 0;
+}
+
+static int clock_control_esp32_on(const struct device *dev,
+				  clock_control_subsys_t sys)
+{
+	ARG_UNUSED(dev);
+	periph_module_enable((periph_module_t)sys);
+	return 0;
+}
+
+static int clock_control_esp32_off(const struct device *dev,
+				   clock_control_subsys_t sys)
+{
+	ARG_UNUSED(dev);
+	periph_module_disable((periph_module_t)sys);
+	return 0;
+}
+
+static int clock_control_esp32_async_on(const struct device *dev,
+					clock_control_subsys_t sys,
+					clock_control_cb_t cb,
+					void *user_data)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(sys);
+	ARG_UNUSED(cb);
+	ARG_UNUSED(user_data);
+	return -ENOTSUP;
+}
+
+static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
+								clock_control_subsys_t sys)
+{
+	ARG_UNUSED(dev);
+	uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
+	uint32_t clk_en_mask =  periph_ll_get_clk_en_mask((periph_module_t)sys);
+
+	if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
+		return CLOCK_CONTROL_STATUS_ON;
+	}
+	return CLOCK_CONTROL_STATUS_OFF;
+}
+
+static int clock_control_esp32_get_rate(const struct device *dev,
+					clock_control_subsys_t sub_system,
+					uint32_t *rate)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(sub_system);
+
+	uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL);
+	uint32_t cpuperiod_sel;
+	uint32_t source_freq_mhz;
+	uint32_t clk_div;
+
+	switch (soc_clk_sel) {
+	case DPORT_SOC_CLK_SEL_XTAL:
+		clk_div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT) + 1;
+		source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
+		*rate = MHZ(source_freq_mhz / clk_div);
+		return 0;
+	case DPORT_SOC_CLK_SEL_PLL:
+		cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
+		if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
+			*rate = MHZ(80);
+		} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
+			*rate = MHZ(160);
+		} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) {
+			*rate = MHZ(240);
+		} else {
+			*rate = 0;
+			return -ENOTSUP;
+		}
+		return 0;
+	case DPORT_SOC_CLK_SEL_8M:
+		*rate = MHZ(8);
+		return 0;
+	default:
+		*rate = 0;
+		return -ENOTSUP;
+	}
+}
+
+static int clock_control_esp32_init(const struct device *dev)
+{
+	struct esp32_clock_config *cfg = DEV_CFG(dev);
+	uint32_t soc_clk_sel = cfg->clk_src_sel;
+	rtc_cpu_freq_config_t cpu_freq_conf;
+
+	if (soc_clk_sel != DPORT_SOC_CLK_SEL_XTAL) {
+		rtc_clk_cpu_freq_to_xtal(ESP32_CLK_CPU_40M, 1);
+	}
+
+	if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL && cfg->cpu_freq != s_cur_pll_freq) {
+		esp_clk_bbpll_disable();
+	}
+
+	switch (cfg->clk_src_sel) {
+	case ESP32_CLK_SRC_XTAL:
+		if (cfg->xtal_freq_sel != ESP32_CLK_XTAL_40M) {
+			return -ENOTSUP;
+		}
+		if (cfg->xtal_div > 1) {
+			rtc_clk_cpu_freq_to_xtal(ESP32_CLK_CPU_40M, cfg->xtal_div);
+		}
+		break;
+	case ESP32_CLK_SRC_PLL:
+		esp_clk_bbpll_enable();
+		rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &cpu_freq_conf);
+		rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), cpu_freq_conf.source_freq_mhz);
+		s_cur_pll_freq = cfg->cpu_freq;
+		esp_clk_cpu_freq_to_pll_mhz(cfg->cpu_freq);
+		break;
+	case ESP32_CLK_SRC_RTC8M:
+		esp_clk_cpu_freq_to_8m();
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct clock_control_driver_api clock_control_esp32_api = {
+	.on = clock_control_esp32_on,
+	.off = clock_control_esp32_off,
+	.async_on = clock_control_esp32_async_on,
+	.get_rate = clock_control_esp32_get_rate,
+	.get_status = clock_control_esp32_get_status,
+};
+
+static const struct esp32_clock_config esp32_clock_config0 = {
+	.clk_src_sel = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_source),
+	.cpu_freq = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_frequency),
+	.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
+	.xtal_div =  DT_INST_PROP(0, xtal_div)
+};
+
+DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
+		 &clock_control_esp32_init,
+		 NULL,
+		 NULL,
+		 &esp32_clock_config0,
+		 PRE_KERNEL_1,
+		 CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
+		 &clock_control_esp32_api);
+
+BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
+		    MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_frequency)),
+		    "SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
+
+BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_source),
+		"CPU clock-source property must be set to ESP32_CLK_SRC_XTAL or ESP32_CLK_SRC_PLL");
diff --git a/dts/bindings/cpu/cadence,tensilica-xtensa-lx7.yaml b/dts/bindings/cpu/cadence,tensilica-xtensa-lx7.yaml
new file mode 100644
index 00000000000..4e3bac07ee4
--- /dev/null
+++ b/dts/bindings/cpu/cadence,tensilica-xtensa-lx7.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cadence Tensilica Xtensa LX7 CPU
+
+compatible: "cdns,tensilica-xtensa-lx7"
+
+include: cpu.yaml
+
+properties:
+    clock-source:
+      type: int
+      description: cpu clock source
+      required: false
diff --git a/dts/xtensa/espressif/esp32s2.dtsi b/dts/xtensa/espressif/esp32s2.dtsi
index 9843416c0a2..64c42bdad66 100644
--- a/dts/xtensa/espressif/esp32s2.dtsi
+++ b/dts/xtensa/espressif/esp32s2.dtsi
@@ -4,7 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <mem.h>
+#include <xtensa/xtensa.dtsi>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/esp32s2_clock.h>
 #include <dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h>
 
 / {
@@ -19,6 +21,7 @@
 			device_type = "cpu";
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <0>;
+			clock-source = <ESP32_CLK_SRC_PLL>;
 		};
 	};
 
@@ -42,6 +45,16 @@
 			status = "okay";
 		};
 
+		rtc: rtc@3f408000 {
+			compatible = "espressif,esp32-rtc";
+			reg = <0x3f408000 0x0D8>;
+			label = "RTC";
+			xtal-freq = <ESP32_CLK_XTAL_40M>;
+			xtal-div = <0>;
+			#clock-cells = <1>;
+			status = "ok";
+		};
+
 		uart0: uart@3f400000 {
 			compatible = "espressif,esp32s2-uart";
 			reg = <0x3f400000 0x400>;
diff --git a/include/dt-bindings/clock/esp32s2_clock.h b/include/dt-bindings/clock/esp32s2_clock.h
new file mode 100644
index 00000000000..8152b68b6c9
--- /dev/null
+++ b/include/dt-bindings/clock/esp32s2_clock.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_
+
+/* System Clock Source */
+#define ESP32_CLK_SRC_XTAL             0U
+#define ESP32_CLK_SRC_PLL              1U
+#define ESP32_CLK_SRC_RTC8M            2U
+#define ESP32_CLK_SRC_APLL             3U
+
+/* Supported CPU Frequencies */
+#define ESP32_CLK_CPU_26M              26U
+#define ESP32_CLK_CPU_40M              40U
+#define ESP32_CLK_CPU_80M              80U
+#define ESP32_CLK_CPU_160M             160U
+#define ESP32_CLK_CPU_240M             240U
+
+/* Supported XTAL Frequencies */
+#define ESP32_CLK_XTAL_40M             0U
+
+/* Modules IDs
+ * These IDs are actually offsets in CLK and RST Control registers.
+ * These IDs shouldn't be changed unless there is a Hardware change
+ * from Espressif.
+ *
+ * Basic Modules
+ * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
+ */
+#define ESP32_LEDC_MODULE              0
+#define ESP32_UART0_MODULE             1
+#define ESP32_UART1_MODULE             2
+#define ESP32_USB_MODULE               3
+#define ESP32_I2C0_MODULE              4
+#define ESP32_I2C1_MODULE              5
+#define ESP32_I2S0_MODULE              6
+#define ESP32_I2S1_MODULE              7
+#define ESP32_TIMG0_MODULE             8
+#define ESP32_TIMG1_MODULE             9
+#define ESP32_PWM0_MODULE              10
+#define ESP32_PWM1_MODULE              11
+#define ESP32_PWM2_MODULE              12
+#define ESP32_PWM3_MODULE              13
+#define ESP32_UHCI0_MODULE             14
+#define ESP32_UHCI1_MODULE             15
+#define ESP32_RMT_MODULE               16
+#define ESP32_PCNT_MODULE              17
+#define ESP32_SPI_MODULE               18
+#define ESP32_FSPI_MODULE              19
+#define ESP32_HSPI_MODULE              20
+#define ESP32_SPI2_DMA_MODULE          21
+#define ESP32_SPI3_DMA_MODULE          22
+#define ESP32_TWAI_MODULE              23
+#define ESP32_RNG_MODULE               24
+#define ESP32_WIFI_MODULE              25
+#define ESP32_WIFI_BT_COMMON_MODULE    26
+#define ESP32_SYSTIMER_MODULE          27
+#define ESP32_AES_MODULE               28
+#define ESP32_SHA_MODULE               29
+#define ESP32_RSA_MODULE               30
+#define ESP32_CRYPTO_DMA_MODULE        31
+#define ESP32_AES_DMA_MODULE           32
+#define ESP32_SHA_DMA_MODULE           33
+#define ESP32_DEDIC_GPIO_MODULE        34
+#define ESP32_MODULE_MAX               35
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_ */
diff --git a/soc/xtensa/esp32s2/Kconfig.soc b/soc/xtensa/esp32s2/Kconfig.soc
index 0da67a7e8cc..75b0cb2a0f7 100644
--- a/soc/xtensa/esp32s2/Kconfig.soc
+++ b/soc/xtensa/esp32s2/Kconfig.soc
@@ -6,6 +6,8 @@ config SOC_ESP32S2
 	select XTENSA
 	select ATOMIC_OPERATIONS_C
 	select DYNAMIC_INTERRUPTS
+	select CLOCK_CONTROL
+	select CLOCK_CONTROL_ESP32S2
 
 if SOC_ESP32S2
 
diff --git a/soc/xtensa/esp32s2/soc.h b/soc/xtensa/esp32s2/soc.h
index 58b5598317e..003d04f685c 100644
--- a/soc/xtensa/esp32s2/soc.h
+++ b/soc/xtensa/esp32s2/soc.h
@@ -9,6 +9,7 @@
 #include <soc/syscon_reg.h>
 #include <soc/system_reg.h>
 #include <soc/dport_access.h>
+#include <soc/rtc_cntl_reg.h>
 #include <soc/soc_caps.h>
 #include <esp32s2/rom/ets_sys.h>
 #include <esp32s2/rom/spi_flash.h>
@@ -38,4 +39,6 @@ extern void esp_rom_Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t
 extern void esp_rom_Cache_Invalidate_ICache_All(void);
 void esp_rom_Cache_Resume_ICache(uint32_t autoload);
 
+extern uint32_t esp_rom_g_ticks_per_us_pro;
+
 #endif /* __SOC_H__ */