diff --git a/dts/arm/adi/max32/max32657.dtsi b/dts/arm/adi/max32/max32657.dtsi
index 0e38c346e9f..b786cfbe77f 100644
--- a/dts/arm/adi/max32/max32657.dtsi
+++ b/dts/arm/adi/max32/max32657.dtsi
@@ -36,6 +36,16 @@
 					erase-block-size = <8192>;
 				};
 			};
+
+			dma1: dma@35000 {
+				compatible = "adi,max32-dma";
+				reg = <0x35000 0x1000>;
+				clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>;
+				interrupts = <20 0>, <21 0>, <22 0>, <23 0>;
+				dma-channels = <4>;
+				status = "disabled";
+				#dma-cells = <2>;
+			};
 		};
 	};
 };
diff --git a/dts/arm/adi/max32/max32657_common.dtsi b/dts/arm/adi/max32/max32657_common.dtsi
index 1a864d871ed..61c3df8ce4d 100644
--- a/dts/arm/adi/max32/max32657_common.dtsi
+++ b/dts/arm/adi/max32/max32657_common.dtsi
@@ -6,6 +6,7 @@
 
 #include <arm/armv8-m.dtsi>
 #include <mem.h>
+#include <zephyr/dt-bindings/dma/max32657_dma.h>
 #include <freq.h>
 
 / {
diff --git a/dts/arm/adi/max32/max32657_ns.dtsi b/dts/arm/adi/max32/max32657_ns.dtsi
index 673ca25b0cf..50cb1eee13e 100644
--- a/dts/arm/adi/max32/max32657_ns.dtsi
+++ b/dts/arm/adi/max32/max32657_ns.dtsi
@@ -20,6 +20,16 @@
 			pinctrl: pin-controller@8000 {
 				ranges = <0x8000 0x40008000 0x1000>;
 			};
+
+			dma0: dma@28000 {
+				compatible = "adi,max32-dma";
+				reg = <0x28000 0x1000>;
+				clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
+				interrupts = <16 0>, <17 0>, <18 0>, <19 0>;
+				dma-channels = <4>;
+				status = "disabled";
+				#dma-cells = <2>;
+			};
 		};
 
 		flc0: flash_controller@50029000 {
diff --git a/include/zephyr/dt-bindings/dma/max32657_dma.h b/include/zephyr/dt-bindings/dma/max32657_dma.h
new file mode 100644
index 00000000000..86d0ab20487
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/max32657_dma.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_
+
+#define MAX32_DMA_SLOT_MEMTOMEM          0x00U
+#define MAX32_DMA_SLOT_SPI_RX            0x01U
+#define MAX32_DMA_SLOT_UART_RX           0x04U
+#define MAX32_DMA_SLOT_I2C_CONTROLLER_RX 0x07U
+#define MAX32_DMA_SLOT_I3C_CONTROLLER_RX 0x07U
+#define MAX32_DMA_SLOT_I2C_TARGET_RX     0x08U
+#define MAX32_DMA_SLOT_I3C_TARGET_RX     0x08U
+#define MAX32_DMA_SLOT_AES_RX            0x10U
+#define MAX32_DMA_SLOT_SPI_TX            0x21U
+#define MAX32_DMA_SLOT_UART_TX           0x24U
+#define MAX32_DMA_SLOT_I2C_CONTROLLER_TX 0x27U
+#define MAX32_DMA_SLOT_I3C_CONTROLLER_TX 0x27U
+#define MAX32_DMA_SLOT_I2C_TARGET_TX     0x28U
+#define MAX32_DMA_SLOT_I3C_TARGET_TX     0x28U
+#define MAX32_DMA_SLOT_CRC               0x2CU
+#define MAX32_DMA_SLOT_AES_TX            0x30U
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_ */