From e58724970481ceb9b3024dc060871a6bdea920df Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 23:47:31 -0300 Subject: [PATCH] soc: espressif: esp32: update to hal_espressif v5.1 Modify and reorganize SoC to meet updated hal. Signed-off-by: Sylvio Alves Signed-off-by: Lucas Tamborrino --- arch/xtensa/core/xtensa_backtrace.c | 2 +- .../zephyr/dt-bindings/clock/esp32_clock.h | 8 +- scripts/west_commands/runners/esp32.py | 6 +- soc/espressif/Kconfig | 39 ++++++ soc/espressif/esp32/CMakeLists.txt | 66 +++------ soc/espressif/esp32/Kconfig | 126 ------------------ soc/espressif/esp32/Kconfig.defconfig | 12 -- soc/espressif/esp32/Kconfig.mac | 45 +++++++ soc/espressif/esp32/Kconfig.rtc | 77 +++++++++++ soc/espressif/esp32/default.ld | 86 +++++++++++- soc/espressif/esp32/esp32-mp.c | 2 +- soc/espressif/esp32/loader.c | 108 --------------- soc/espressif/esp32/mcuboot.ld | 9 +- soc/espressif/esp32/soc.c | 126 ++++++------------ soc/espressif/esp32/soc.h | 2 +- soc/espressif/esp32/soc_appcpu.c | 83 ++---------- 16 files changed, 331 insertions(+), 466 deletions(-) create mode 100644 soc/espressif/esp32/Kconfig.mac create mode 100644 soc/espressif/esp32/Kconfig.rtc delete mode 100644 soc/espressif/esp32/loader.c diff --git a/arch/xtensa/core/xtensa_backtrace.c b/arch/xtensa/core/xtensa_backtrace.c index 5871a10c48f..8570fa5dbd6 100644 --- a/arch/xtensa/core/xtensa_backtrace.c +++ b/arch/xtensa/core/xtensa_backtrace.c @@ -8,7 +8,7 @@ #include "xtensa_backtrace.h" #include #if defined(CONFIG_SOC_SERIES_ESP32) -#include "soc/soc_memory_layout.h" +#include #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) #include "debug_helpers.h" #elif defined(CONFIG_SOC_XTENSA_DC233C) diff --git a/include/zephyr/dt-bindings/clock/esp32_clock.h b/include/zephyr/dt-bindings/clock/esp32_clock.h index 65ca36c3609..99ab3c7004b 100644 --- a/include/zephyr/dt-bindings/clock/esp32_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32_clock.h @@ -22,10 +22,10 @@ #define ESP32_CLK_CPU_240M 240000000 /* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_24M 0U -#define ESP32_CLK_XTAL_26M 1U -#define ESP32_CLK_XTAL_40M 2U -#define ESP32_CLK_XTAL_AUTO 3U +#define ESP32_CLK_XTAL_24M 24 +#define ESP32_CLK_XTAL_26M 26 +#define ESP32_CLK_XTAL_40M 40 +#define ESP32_CLK_XTAL_AUTO 0 /* Supported RTC fast clock frequencies */ #define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U diff --git a/scripts/west_commands/runners/esp32.py b/scripts/west_commands/runners/esp32.py index 0ccf0c98d1f..b68ddd9b2f7 100644 --- a/scripts/west_commands/runners/esp32.py +++ b/scripts/west_commands/runners/esp32.py @@ -71,7 +71,7 @@ class Esp32BinaryRunner(ZephyrBinaryRunner): parser.add_argument( '--esp-tool', help='''if given, complete path to espidf. default is to search for - it in [ESP_IDF_PATH]/components/esptool_py/esptool/esptool.py''') + it in [ESP_IDF_PATH]/tools/esptool_py/esptool.py''') parser.add_argument('--esp-flash-bootloader', help='Bootloader image to flash') parser.add_argument('--esp-flash-partition_table', @@ -86,8 +86,8 @@ class Esp32BinaryRunner(ZephyrBinaryRunner): if args.esp_tool: espidf = args.esp_tool else: - espidf = path.join(args.esp_idf_path, 'components', 'esptool_py', - 'esptool', 'esptool.py') + espidf = path.join(args.esp_idf_path, 'tools', 'esptool_py', + 'esptool.py') return Esp32BinaryRunner( cfg, args.esp_device, boot_address=args.esp_boot_address, diff --git a/soc/espressif/Kconfig b/soc/espressif/Kconfig index 3c96a64bff6..1917c3b432b 100644 --- a/soc/espressif/Kconfig +++ b/soc/espressif/Kconfig @@ -5,4 +5,43 @@ if SOC_FAMILY_ESPRESSIF_ESP32 rsource "*/Kconfig" +menu "MAC Config" + +config ESP_MAC_ADDR_UNIVERSE_WIFI_STA + bool + +config ESP_MAC_ADDR_UNIVERSE_WIFI_AP + bool + +config ESP_MAC_ADDR_UNIVERSE_ETH + bool + +config ESP_MAC_ADDR_UNIVERSE_BT + bool + +config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE + bool + +config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO + bool + +config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR + bool + +# Insert chip-specific MAC config +rsource "*/Kconfig.mac" + +endmenu + +menu "RTC Clock Config" + +config ESP_SYSTEM_RTC_EXT_XTAL + bool + +config ESP_SYSTEM_RTC_EXT_OSC + bool + +rsource "*/Kconfig.rtc" +endmenu + endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/esp32/CMakeLists.txt b/soc/espressif/esp32/CMakeLists.txt index 537c7c76acc..b1ad883b3e3 100644 --- a/soc/espressif/esp32/CMakeLists.txt +++ b/soc/espressif/esp32/CMakeLists.txt @@ -1,12 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_ESP32_APPCPU) +if (CONFIG_SOC_ESP32_APPCPU) zephyr_sources(soc_appcpu.c) else() zephyr_sources( soc.c - loader.c esp32-mp.c + ../common/loader.c ) endif() @@ -23,60 +23,31 @@ zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) + set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) + if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") + endif() - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) + if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") + endif() + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + endif() if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py ARGS --chip esp32 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) @@ -85,10 +56,12 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) if(CONFIG_MCUBOOT) board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") endif() + endif() ## When building for APPCPU -if(CONFIG_SOC_ESP32_APPCPU) +if (CONFIG_SOC_ESP32_APPCPU) + if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py @@ -96,6 +69,7 @@ if(CONFIG_SOC_ESP32_APPCPU) -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c -a "esp32_appcpu_fw_array") endif() + else() set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) diff --git a/soc/espressif/esp32/Kconfig b/soc/espressif/esp32/Kconfig index 26305dd553f..67df8e255a5 100644 --- a/soc/espressif/esp32/Kconfig +++ b/soc/espressif/esp32/Kconfig @@ -41,12 +41,6 @@ config SOC_ENABLE_APPCPU help This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled. -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - config ESP32_BT_RESERVE_DRAM hex "Bluetooth controller reserved RAM region" default 0xdb5c if BT @@ -63,77 +57,6 @@ config ESP_HEAP_MEM_POOL_REGION_1_SIZE This configuration can be used to add memory from region 1 to heap and can be allocated using k_malloc. -choice ESP32_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 150kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8.5MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 150kHz oscillator. It does not require external components. - -config ESP32_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - -config ESP32_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" - -endchoice # ESP32_RTC_CLK_SRC - -config ESP32_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config ESP32_RTC_XTAL_CAL_RETRY - int "Number of attempts to repeat 32k XTAL calibration" - default 1 - depends on ESP32_RTC_CLK_SRC_EXT_CRYS - help - Number of attempts to repeat 32k XTAL calibration - before giving up and switching to the internal RC. - Increase this option if the 32k crystal oscillator - does not start and switches to internal RC. - config ESP32_DEEP_SLEEP_WAKEUP_DELAY int "Extra delay in deep sleep wake stub (in us)" default 2000 @@ -152,55 +75,6 @@ config ESP32_DEEP_SLEEP_WAKEUP_DELAY If you are seeing "flash read err, 1000" message printed to the console after deep sleep reset, try increasing this value. -choice ESP32_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is four, - all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally - administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) - to the final octet of the base MAC address. If the number of universal MAC addresses is two, - only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. - These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. - The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. - These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 2 or 4 per device.) - -config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_BT - -config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - bool "Four" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - select ESP_MAC_ADDR_UNIVERSE_BT - select ESP_MAC_ADDR_UNIVERSE_ETH - -endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP_MAC_ADDR_UNIVERSE_BT - bool - -config ESP_MAC_ADDR_UNIVERSE_ETH - bool - -config ESP32_UNIVERSAL_MAC_ADDRESSES - int - default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - config ESP32_PHY_MAX_WIFI_TX_POWER int "Max WiFi/BLE TX power (dBm)" range 10 20 diff --git a/soc/espressif/esp32/Kconfig.defconfig b/soc/espressif/esp32/Kconfig.defconfig index 17bda587b97..74f7949e714 100644 --- a/soc/espressif/esp32/Kconfig.defconfig +++ b/soc/espressif/esp32/Kconfig.defconfig @@ -3,18 +3,6 @@ if SOC_SERIES_ESP32 -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - config FLASH_SIZE default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0) diff --git a/soc/espressif/esp32/Kconfig.mac b/soc/espressif/esp32/Kconfig.mac new file mode 100644 index 00000000000..b149bc5e905 --- /dev/null +++ b/soc/espressif/esp32/Kconfig.mac @@ -0,0 +1,45 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 + +choice ESP32_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is four, + all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally + administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) + to the final octet of the base MAC address. If the number of universal MAC addresses is two, + only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. + These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. + The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. + These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 2 or 4 per device.) + +config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES + +config ESP32_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + +endif # SOC_SERIES_ESP32 diff --git a/soc/espressif/esp32/Kconfig.rtc b/soc/espressif/esp32/Kconfig.rtc new file mode 100644 index 00000000000..bfbddc28ebb --- /dev/null +++ b/soc/espressif/esp32/Kconfig.rtc @@ -0,0 +1,77 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 + +choice RTC_CLK_SRC + prompt "RTC clock source" + default RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + - "Internal 150kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8.5MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 150kHz oscillator. It does not require external components. + +config RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + +config RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config RTC_CLK_SRC_INT_8MD256 + bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" + +endchoice # RTC_CLK_SRC + +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 1024 if RTC_CLK_SRC_INT_RC + range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + range 0 32766 if RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +config RTC_XTAL_CAL_RETRY + int "Number of attempts to repeat 32k XTAL calibration" + default 1 + depends on RTC_CLK_SRC_EXT_CRYS + help + Number of attempts to repeat 32k XTAL calibration + before giving up and switching to the internal RC. + Increase this option if the 32k crystal oscillator + does not start and switches to internal RC. + +endif # SOC_SERIES_ESP32 diff --git a/soc/espressif/esp32/default.ld b/soc/espressif/esp32/default.ld index a3577757dcd..a4210b3cc74 100644 --- a/soc/espressif/esp32/default.ld +++ b/soc/espressif/esp32/default.ld @@ -18,10 +18,10 @@ #include #define RAMABLE_REGION dram0_0_seg -#ifndef CONFIG_SOC_ENABLE_APPCPU -#define RAMABLE_REGION_1 dram0_1_seg -#else +#ifdef CONFIG_SOC_ENABLE_APPCPU #define RAMABLE_REGION_1 dram0_0_seg +#else +#define RAMABLE_REGION_1 dram0_1_seg #endif #define RODATA_REGION drom0_0_seg #define IRAM_REGION iram0_0_seg @@ -165,6 +165,7 @@ SECTIONS SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) { __rodata_region_start = ABSOLUTE(.); + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ . = ALIGN(4); #include @@ -224,6 +225,7 @@ SECTIONS { . = ALIGN(4); _image_rodata_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) _image_dram_start = LOADADDR(.dram0.data); @@ -259,10 +261,38 @@ SECTIONS *libzephyr.a:log_core.*(.rodata .rodata.*) *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) *libzephyr.a:loader.*(.rodata .rodata.*) *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:cache_esp32.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_cache.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_err.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_slave_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:heap_caps_zephyr.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) KEEP(*(.jcr)) *(.dram1 .dram1.*) @@ -363,12 +393,54 @@ SECTIONS *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) *libc.a:*(.literal .text .literal.* .text.*) *libphy.a:( .phyiram .phyiram.*) *libgcov.a:(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *libzephyr.a:cpu.*(.literal.esp_cpu_reset .text.esp_cpu_reset) + *libzephyr.a:cpu.*(.literal.esp_cpu_stall .text.esp_cpu_stall) + *libzephyr.a:cpu.*(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *libzephyr.a:cpu.*(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:periph_ctrl.*(.literal.periph_module_reset .text.periph_module_reset) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_disable .text.wifi_module_disable) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_enable .text.wifi_module_enable) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_wdt.*(.literal .literal.* .text .text.*) + *libzephyr.a:sar_periph_ctrl.*(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + *libzephyr.a:cache_esp32.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_system_chip.*(.literal.esp_system_abort .text.esp_system_abort) + *libzephyr.a:i2c_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:mmu_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_slave_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:heap_caps_zephyr.*(.literal .literal.* .text .text.*) #if defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) @@ -445,11 +517,13 @@ SECTIONS *libsubsys__net__ip.a:(.noinit .noinit.*) *libsubsys__net.a:(.noinit .noinit.*) #endif + _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + _ext_ram_bss_end = ABSOLUTE(.); + _spiram_heap_start = ABSOLUTE(.); . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; - *(.ext_ram.bss*) - _ext_ram_data_end = ABSOLUTE(.); } GROUP_LINK_IN(ext_ram_seg) #endif @@ -506,6 +580,7 @@ SECTIONS .flash.text : ALIGN(IROM_SEG_ALIGN) { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ _text_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) @@ -521,6 +596,7 @@ SECTIONS *(.literal .text .literal.* .text.*) . = ALIGN(4); _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; /* Similar to _iram_start, this symbol goes here so it is diff --git a/soc/espressif/esp32/esp32-mp.c b/soc/espressif/esp32/esp32-mp.c index baaae7020d6..c380df6c8b7 100644 --- a/soc/espressif/esp32/esp32-mp.c +++ b/soc/espressif/esp32/esp32-mp.c @@ -88,7 +88,7 @@ static void appcpu_entry2(void) * later. */ __asm__ volatile("rsr.PS %0" : "=r"(ps)); - ps &= ~(PS_EXCM_MASK | PS_INTLEVEL_MASK); + ps &= ~(XCHAL_PS_EXCM_MASK | XCHAL_PS_INTLEVEL_MASK); __asm__ volatile("wsr.PS %0" : : "r"(ps)); ie = 0; diff --git a/soc/espressif/esp32/loader.c b/soc/espressif/esp32/loader.c deleted file mode 100644 index 5b946bfba41..00000000000 --- a/soc/espressif/esp32/loader.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_BOOTLOADER_MCUBOOT - -#define BOOT_LOG_INF(_fmt, ...) \ - ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) - -#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) - -extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; -extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; - -void __start(void); - -static HDR_ATTR void (*_entry_point)(void) = &__start; - -static int map_rom_segments(void) -{ - int rc = 0; - size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); - uint32_t _app_irom_start = _partition_offset + - (uint32_t)&_image_irom_start; - uint32_t _app_irom_size = (uint32_t)&_image_irom_size; - uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr; - - uint32_t _app_drom_start = _partition_offset + - (uint32_t)&_image_drom_start; - uint32_t _app_drom_size = (uint32_t)&_image_drom_size; - uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr; - - Cache_Read_Disable(0); - Cache_Flush(0); - /* Clear the MMU entries that are already set up, - * so the new app only has the mappings it creates. - */ - for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) { - DPORT_PRO_FLASH_MMU_TABLE[i] = - DPORT_FLASH_MMU_TABLE_INVALID_VAL; - } - - uint32_t drom_vaddr_addr_aligned = _app_drom_vaddr & MMU_FLASH_MASK; - uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, - _app_drom_vaddr); - rc = cache_flash_mmu_set(0, 0, drom_vaddr_addr_aligned, _app_drom_start - & MMU_FLASH_MASK, 64, drom_page_count); - rc |= cache_flash_mmu_set(1, 0, drom_vaddr_addr_aligned, _app_drom_start - & MMU_FLASH_MASK, 64, drom_page_count); - - uint32_t irom_vaddr_addr_aligned = _app_irom_vaddr & MMU_FLASH_MASK; - uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, - _app_irom_vaddr); - rc |= cache_flash_mmu_set(0, 0, irom_vaddr_addr_aligned, _app_irom_start - & MMU_FLASH_MASK, 64, irom_page_count); - rc |= cache_flash_mmu_set(1, 0, irom_vaddr_addr_aligned, _app_irom_start - & MMU_FLASH_MASK, 64, irom_page_count); - - DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, - (DPORT_PRO_CACHE_MASK_IRAM0) | - (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | - (DPORT_PRO_CACHE_MASK_IROM0 & 0) | - DPORT_PRO_CACHE_MASK_DROM0 | - DPORT_PRO_CACHE_MASK_DRAM1); - - DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, - (DPORT_APP_CACHE_MASK_IRAM0) | - (DPORT_APP_CACHE_MASK_IRAM1 & 0) | - (DPORT_APP_CACHE_MASK_IROM0 & 0) | - DPORT_APP_CACHE_MASK_DROM0 | - DPORT_APP_CACHE_MASK_DRAM1); - - esp_rom_Cache_Read_Enable(0); - - /* Show map segments continue using same log format as during MCUboot phase */ - BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", - _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); - BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", - _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); - esp_rom_uart_tx_wait_idle(0); - - return rc; -} -#endif - -void __start(void) -{ -#ifdef CONFIG_BOOTLOADER_MCUBOOT - int err = map_rom_segments(); - - if (err != 0) { - ets_printf("Failed to setup XIP, aborting\n"); - abort(); - } -#endif - __esp_platform_start(); -} diff --git a/soc/espressif/esp32/mcuboot.ld b/soc/espressif/esp32/mcuboot.ld index a3b2af762dd..d30e1e8c68d 100644 --- a/soc/espressif/esp32/mcuboot.ld +++ b/soc/espressif/esp32/mcuboot.ld @@ -38,7 +38,7 @@ MEMORY { iram_loader_seg (RWX) : org = 0x40078000, len = 0x4000 iram_seg (RWX) : org = 0x4009C000, len = 0x8000 - dram_seg (RW) : org = 0x3FFF0000, len = 0x6000 + dram_seg (RW) : org = 0x3FFF0000, len = 0x6400 #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -132,6 +132,8 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) KEEP(*(.jcr)) *(.dram1 .dram1.*) @@ -235,6 +237,11 @@ SECTIONS *libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*) *esp_mcuboot.*(.literal .text .literal.* .text.*) *esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *(.fini.literal) *(.fini) *(.gnu.version) diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c index 8e1a8ff737a..280b8da3a6e 100644 --- a/soc/espressif/esp32/soc.c +++ b/soc/espressif/esp32/soc.c @@ -11,6 +11,12 @@ #include #include #include +#include +#include +#if CONFIG_ESP_SPIRAM +#include +#include +#endif #include #include @@ -19,17 +25,16 @@ #include #include -#include "esp_private/system_internal.h" -#include "esp32/rom/cache.h" -#include "hal/soc_ll.h" -#include "soc/cpu.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_err.h" -#include "esp_timer.h" -#include "esp32/spiram.h" -#include "esp_app_format.h" -#include "hal/wdt_hal.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #ifndef CONFIG_SOC_ENABLE_APPCPU #include "esp_clk_internal.h" @@ -40,6 +45,11 @@ #endif /* CONFIG_MCUBOOT */ #include +#if CONFIG_ESP_SPIRAM +extern int _ext_ram_bss_start; +extern int _ext_ram_bss_end; +#endif + extern void z_cstart(void); extern void esp_reset_reason_init(void); @@ -115,7 +125,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) * initialization code wants a valid _current before * arch_kernel_init() is invoked. */ - __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); esp_reset_reason_init(); @@ -135,7 +145,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) wdt_hal_disable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx); -#ifdef CONFIG_SOC_ESP32_APPCPU +#ifndef CONFIG_SOC_ENABLE_APPCPU /* Configures the CPU clock, RTC slow and fast clocks, and performs * RTC slow clock calibration. */ @@ -149,18 +159,34 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) esp_start_appcpu(); #endif + esp_mmu_map_init(); + +#ifdef CONFIG_SOC_FLASH_ESP32 + esp_mspi_pin_init(); + spi_flash_init_chip_state(); +#endif + #if CONFIG_ESP_SPIRAM - esp_err_t err = esp_spiram_init(); + esp_err_t err = esp_psram_init(); if (err != ESP_OK) { printk("Failed to Initialize SPIRAM, aborting.\n"); abort(); } - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + if (esp_psram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { printk("SPIRAM size is less than configured size, aborting.\n"); abort(); } + + if (esp_psram_is_initialized()) { + if (!esp_psram_extram_test()) { + printk("External RAM failed memory test!"); + abort(); + } + } + + memset(&_ext_ram_bss_start, 0, + (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); #endif /* Scheduler is not started at this point. Hence, guard functions @@ -196,71 +222,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* Disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - const uint32_t core_id = cpu_hal_get_core_id(); - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Read_Disable(0); - Cache_Read_Disable(1); - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | - DPORT_BT_RST | DPORT_BTMAC_RST | - DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | - DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - DPORT_SET_PERI_REG_MASK( - DPORT_PERIP_RST_EN_REG, - /* UART TX FIFO cannot be reset correctly on ESP32, */ - /* so reset the UART memory by DPORT here. */ - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | - DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); - - /* Clear entry point for APP CPU */ - DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -} diff --git a/soc/espressif/esp32/soc.h b/soc/espressif/esp32/soc.h index 473d6e750a3..e2ea8cc50b7 100644 --- a/soc/espressif/esp32/soc.h +++ b/soc/espressif/esp32/soc.h @@ -18,7 +18,7 @@ #include #include -#include +#include void __esp_platform_start(void); diff --git a/soc/espressif/esp32/soc_appcpu.c b/soc/espressif/esp32/soc_appcpu.c index a8ff116a58a..146a37087c8 100644 --- a/soc/espressif/esp32/soc_appcpu.c +++ b/soc/espressif/esp32/soc_appcpu.c @@ -20,13 +20,16 @@ #include #include -#include -#include -#include +#include +#include +#include +#include +#include +#include #include -#include +#include #include -#include +#include #include #include @@ -68,7 +71,7 @@ void __app_cpu_start(void) * initialization code wants a valid _current before * arch_kernel_init() is invoked. */ - __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); esp_intr_initialize(); /* Start Zephyr */ @@ -88,71 +91,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* Disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - const uint32_t core_id = cpu_hal_get_core_id(); - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Read_Disable(0); - Cache_Read_Disable(1); - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | - DPORT_BT_RST | DPORT_BTMAC_RST | - DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | - DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - DPORT_SET_PERI_REG_MASK( - DPORT_PERIP_RST_EN_REG, - /* UART TX FIFO cannot be reset correctly on ESP32, */ - /* so reset the UART memory by DPORT here. */ - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | - DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); - - /* Clear entry point for APP CPU */ - DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -}