drivers: spi: gd32: Add support DMA transfer
Add supporting DMA-based transfer for GD32 SPI. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi
Marti Bolivar
parent
b5bfd3b12c
commit
e55cbb8ce6
2 changed files with 324 additions and 5 deletions
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@ -13,7 +13,16 @@ if SPI_GD32
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config SPI_GD32_INTERRUPT
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bool "GD32 MCU SPI Interrupt Support"
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default y if SPI_ASYNC
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default y if SPI_GD32_DMA
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help
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Enable the interrupt driven mode for SPI instances
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config SPI_GD32_DMA
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bool "GD32 MCU SPI DMA Support"
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select DMA
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select SPI_GD32_INTERRUPT
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help
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Use the DMA for SPI transfer
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that enable dma channels in their device tree node.
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endif # SPI_GD32
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@ -13,6 +13,10 @@
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/drivers/spi.h>
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#ifdef CONFIG_SPI_GD32_DMA
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/dma/dma_gd32.h>
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#endif
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#include <gd32_spi.h>
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@ -37,11 +41,39 @@ LOG_MODULE_REGISTER(spi_gd32);
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#else
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#error Unknown GD32 soc series
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#endif
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#ifdef CONFIG_SPI_GD32_DMA
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enum spi_gd32_dma_direction {
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RX = 0,
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TX,
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NUM_OF_DIRECTION
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};
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struct spi_gd32_dma_config {
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const struct device *dev;
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uint32_t channel;
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uint32_t config;
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uint32_t slot;
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uint32_t fifo_threshold;
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};
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struct spi_gd32_dma_data {
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struct dma_config config;
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struct dma_block_config block;
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uint32_t count;
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};
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#endif
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struct spi_gd32_config {
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uint32_t reg;
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uint16_t clkid;
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struct reset_dt_spec reset;
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const struct pinctrl_dev_config *pcfg;
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#ifdef CONFIG_SPI_GD32_DMA
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const struct spi_gd32_dma_config dma[NUM_OF_DIRECTION];
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#endif
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#ifdef CONFIG_SPI_GD32_INTERRUPT
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void (*irq_configure)();
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#endif
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@ -49,8 +81,34 @@ struct spi_gd32_config {
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struct spi_gd32_data {
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struct spi_context ctx;
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#ifdef CONFIG_SPI_GD32_DMA
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struct spi_gd32_dma_data dma[NUM_OF_DIRECTION];
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#endif
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};
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#ifdef CONFIG_SPI_GD32_DMA
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static uint32_t dummy_tx;
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static uint32_t dummy_rx;
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static bool spi_gd32_dma_enabled(const struct device *dev)
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{
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const struct spi_gd32_config *cfg = dev->config;
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if (cfg->dma[TX].dev && cfg->dma[RX].dev) {
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return true;
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}
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return false;
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}
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static size_t spi_gd32_dma_enabled_num(const struct device *dev)
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{
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return spi_gd32_dma_enabled(dev) ? 2 : 0;
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}
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#endif
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static int spi_gd32_get_err(const struct spi_gd32_config *cfg)
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{
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uint32_t stat = SPI_STAT(cfg->reg);
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@ -195,6 +253,114 @@ static int spi_gd32_frame_exchange(const struct device *dev)
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return spi_gd32_get_err(cfg);
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}
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#ifdef CONFIG_SPI_GD32_DMA
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static void spi_gd32_dma_callback(const struct device *dma_dev, void *arg,
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uint32_t channel, int status);
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static uint32_t spi_gd32_dma_setup(const struct device *dev, const uint32_t dir)
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{
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const struct spi_gd32_config *cfg = dev->config;
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struct spi_gd32_data *data = dev->data;
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struct dma_config *dma_cfg = &data->dma[dir].config;
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struct dma_block_config *block_cfg = &data->dma[dir].block;
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const struct spi_gd32_dma_config *dma = &cfg->dma[dir];
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int ret;
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memset(dma_cfg, 0, sizeof(struct dma_config));
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memset(block_cfg, 0, sizeof(struct dma_block_config));
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dma_cfg->source_burst_length = 1;
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dma_cfg->dest_burst_length = 1;
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dma_cfg->user_data = (void *)dev;
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dma_cfg->dma_callback = spi_gd32_dma_callback;
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dma_cfg->block_count = 1U;
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dma_cfg->head_block = block_cfg;
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dma_cfg->dma_slot = cfg->dma[dir].slot;
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dma_cfg->channel_priority =
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GD32_DMA_CONFIG_PRIORITY(cfg->dma[dir].config);
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dma_cfg->channel_direction =
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dir == TX ? MEMORY_TO_PERIPHERAL : PERIPHERAL_TO_MEMORY;
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if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
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dma_cfg->source_data_size = 1;
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dma_cfg->dest_data_size = 1;
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} else {
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dma_cfg->source_data_size = 2;
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dma_cfg->dest_data_size = 2;
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}
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block_cfg->block_size = spi_context_max_continuous_chunk(&data->ctx);
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if (dir == TX) {
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block_cfg->dest_address = (uint32_t)&SPI_DATA(cfg->reg);
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block_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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if (spi_context_tx_buf_on(&data->ctx)) {
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block_cfg->source_address = (uint32_t)data->ctx.tx_buf;
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block_cfg->source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
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} else {
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block_cfg->source_address = (uint32_t)&dummy_tx;
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block_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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}
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}
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if (dir == RX) {
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block_cfg->source_address = (uint32_t)&SPI_DATA(cfg->reg);
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block_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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if (spi_context_rx_buf_on(&data->ctx)) {
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block_cfg->dest_address = (uint32_t)data->ctx.rx_buf;
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block_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
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} else {
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block_cfg->dest_address = (uint32_t)&dummy_rx;
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block_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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}
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}
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ret = dma_config(dma->dev, dma->channel, dma_cfg);
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if (ret < 0) {
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LOG_ERR("dma_config %p failed %d\n", dma->dev, ret);
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return ret;
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}
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ret = dma_start(dma->dev, dma->channel);
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if (ret < 0) {
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LOG_ERR("dma_start %p failed %d\n", dma->dev, ret);
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return ret;
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}
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return 0;
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}
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static int spi_gd32_start_dma_transceive(const struct device *dev)
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{
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const struct spi_gd32_config *cfg = dev->config;
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struct spi_gd32_data *data = dev->data;
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const size_t chunk_len = spi_context_max_continuous_chunk(&data->ctx);
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struct dma_status stat;
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int ret = 0;
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for (size_t i = 0; i < spi_gd32_dma_enabled_num(dev); i++) {
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dma_get_status(cfg->dma[i].dev, cfg->dma[i].channel, &stat);
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if ((chunk_len != data->dma[i].count) && !stat.busy) {
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ret = spi_gd32_dma_setup(dev, i);
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if (ret < 0) {
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goto on_error;
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}
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}
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}
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SPI_CTL1(cfg->reg) |= (SPI_CTL1_DMATEN | SPI_CTL1_DMAREN);
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on_error:
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if (ret < 0) {
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for (size_t i = 0; i < spi_gd32_dma_enabled_num(dev); i++) {
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dma_stop(cfg->dma[i].dev, cfg->dma[i].channel);
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}
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}
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return ret;
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}
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#endif
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static int spi_gd32_transceive_impl(const struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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@ -220,8 +386,24 @@ static int spi_gd32_transceive_impl(const struct device *dev,
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spi_context_cs_control(&data->ctx, true);
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#ifdef CONFIG_SPI_GD32_INTERRUPT
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SPI_STAT(cfg->reg) &= ~(SPI_STAT_RBNE | SPI_STAT_TBE | SPI_GD32_ERR_MASK);
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SPI_CTL1(cfg->reg) |= (SPI_CTL1_RBNEIE | SPI_CTL1_TBEIE | SPI_CTL1_ERRIE);
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#ifdef CONFIG_SPI_GD32_DMA
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if (spi_gd32_dma_enabled(dev)) {
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for (size_t i = 0; i < ARRAY_SIZE(data->dma); i++) {
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data->dma[i].count = 0;
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}
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ret = spi_gd32_start_dma_transceive(dev);
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if (ret < 0) {
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goto dma_error;
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}
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} else
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#endif
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{
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SPI_STAT(cfg->reg) &=
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~(SPI_STAT_RBNE | SPI_STAT_TBE | SPI_GD32_ERR_MASK);
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SPI_CTL1(cfg->reg) |=
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(SPI_CTL1_RBNEIE | SPI_CTL1_TBEIE | SPI_CTL1_ERRIE);
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}
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ret = spi_context_wait_for_completion(&data->ctx);
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#else
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do {
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@ -241,9 +423,13 @@ static int spi_gd32_transceive_impl(const struct device *dev,
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/* Wait until last frame transfer complete. */
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}
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#ifdef CONFIG_SPI_GD32_DMA
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dma_error:
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#endif
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spi_context_cs_control(&data->ctx, false);
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SPI_CTL0(cfg->reg) &= ~SPI_CTL0_SPIEN;
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SPI_CTL0(cfg->reg) &=
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~(SPI_CTL0_SPIEN | SPI_CTL1_DMATEN | SPI_CTL1_DMAREN);
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error:
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spi_context_release(&data->ctx, ret);
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@ -278,7 +464,14 @@ static void spi_gd32_complete(const struct device *dev, int status)
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struct spi_gd32_data *data = dev->data;
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const struct spi_gd32_config *cfg = dev->config;
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SPI_CTL1(cfg->reg) &= ~(SPI_CTL1_RBNEIE | SPI_CTL1_TBEIE | SPI_CTL1_ERRIE);
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SPI_CTL1(cfg->reg) &=
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~(SPI_CTL1_RBNEIE | SPI_CTL1_TBEIE | SPI_CTL1_ERRIE);
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#ifdef CONFIG_SPI_GD32_DMA
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for (size_t i = 0; i < spi_gd32_dma_enabled_num(dev); i++) {
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dma_stop(cfg->dma[i].dev, cfg->dma[i].channel);
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}
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#endif
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spi_context_complete(&data->ctx, dev, status);
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}
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@ -302,7 +495,76 @@ static void spi_gd32_isr(struct device *dev)
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SPI_STAT(cfg->reg) = 0;
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}
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#endif /* INTERRUPT */
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#endif /* SPI_GD32_INTERRUPT */
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#ifdef CONFIG_SPI_GD32_DMA
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static bool spi_gd32_chunk_transfer_finished(const struct device *dev)
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{
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struct spi_gd32_data *data = dev->data;
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struct spi_gd32_dma_data *dma = data->dma;
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const size_t chunk_len = spi_context_max_continuous_chunk(&data->ctx);
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return (MIN(dma[TX].count, dma[RX].count) >= chunk_len);
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}
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static void spi_gd32_dma_callback(const struct device *dma_dev, void *arg,
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uint32_t channel, int status)
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{
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const struct device *dev = (const struct device *)arg;
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const struct spi_gd32_config *cfg = dev->config;
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struct spi_gd32_data *data = dev->data;
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const size_t chunk_len = spi_context_max_continuous_chunk(&data->ctx);
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int err = 0;
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if (status < 0) {
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LOG_ERR("dma:%p ch:%d callback gets error: %d", dma_dev, channel,
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status);
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spi_gd32_complete(dev, status);
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return;
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}
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for (size_t i = 0; i < ARRAY_SIZE(cfg->dma); i++) {
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if (dma_dev == cfg->dma[i].dev &&
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channel == cfg->dma[i].channel) {
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data->dma[i].count += chunk_len;
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}
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}
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/* Check transfer finished.
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* The transmission of this chunk is complete if both the dma[TX].count
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* and the dma[RX].count reach greater than or equal to the chunk_len.
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* chunk_len is zero here means the transfer is already complete.
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*/
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if (spi_gd32_chunk_transfer_finished(dev)) {
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if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
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spi_context_update_tx(&data->ctx, 1, chunk_len);
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spi_context_update_rx(&data->ctx, 1, chunk_len);
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} else {
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spi_context_update_tx(&data->ctx, 2, chunk_len);
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spi_context_update_rx(&data->ctx, 2, chunk_len);
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}
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if (spi_gd32_transfer_ongoing(data)) {
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/* Next chunk is available, reset the count and
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* continue processing
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*/
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data->dma[TX].count = 0;
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data->dma[RX].count = 0;
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} else {
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/* All data is processed, complete the process */
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spi_context_complete(&data->ctx, dev, 0);
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return;
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}
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}
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err = spi_gd32_start_dma_transceive(dev);
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if (err) {
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spi_gd32_complete(dev, err);
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}
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}
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#endif /* DMA */
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static int spi_gd32_release(const struct device *dev,
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const struct spi_config *config)
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@ -327,6 +589,9 @@ int spi_gd32_init(const struct device *dev)
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struct spi_gd32_data *data = dev->data;
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const struct spi_gd32_config *cfg = dev->config;
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int ret;
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#ifdef CONFIG_SPI_GD32_DMA
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uint32_t ch_filter;
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#endif
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(void)clock_control_on(GD32_CLOCK_CONTROLLER,
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(clock_control_subsys_t *)&cfg->clkid);
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@ -339,6 +604,28 @@ int spi_gd32_init(const struct device *dev)
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return ret;
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}
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#ifdef CONFIG_SPI_GD32_DMA
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if ((cfg->dma[RX].dev && !cfg->dma[TX].dev) ||
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(cfg->dma[TX].dev && !cfg->dma[RX].dev)) {
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LOG_ERR("DMA must be enabled for both TX and RX channels");
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return -ENODEV;
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}
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for (size_t i = 0; i < spi_gd32_dma_enabled_num(dev); i++) {
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if (!device_is_ready(cfg->dma[i].dev)) {
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LOG_ERR("DMA %s not ready", cfg->dma[i].dev->name);
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return -ENODEV;
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}
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ch_filter = BIT(cfg->dma[i].channel);
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ret = dma_request_channel(cfg->dma[i].dev, &ch_filter);
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if (ret < 0) {
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LOG_ERR("dma_request_channel failed %d", ret);
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return ret;
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}
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}
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#endif
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ret = spi_context_cs_configure_all(&data->ctx);
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if (ret < 0) {
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return ret;
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@ -353,6 +640,28 @@ int spi_gd32_init(const struct device *dev)
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return 0;
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}
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#define DMA_INITIALIZER(idx, dir) \
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{ \
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.dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(idx, dir)), \
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.channel = DT_INST_DMAS_CELL_BY_NAME(idx, dir, channel), \
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.slot = COND_CODE_1( \
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DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1), \
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(DT_INST_DMAS_CELL_BY_NAME(idx, dir, slot)), (0)), \
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.config = DT_INST_DMAS_CELL_BY_NAME(idx, dir, config), \
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.fifo_threshold = COND_CODE_1( \
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DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1), \
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(DT_INST_DMAS_CELL_BY_NAME(idx, dir, fifo_threshold)), \
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(0)), \
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}
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#define DMAS_DECL(idx) \
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{ \
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COND_CODE_1(DT_INST_DMAS_HAS_NAME(idx, rx), \
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(DMA_INITIALIZER(idx, rx)), ({0})), \
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COND_CODE_1(DT_INST_DMAS_HAS_NAME(idx, tx), \
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(DMA_INITIALIZER(idx, tx)), ({0})), \
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}
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#define GD32_IRQ_CONFIGURE(idx) \
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static void spi_gd32_irq_configure_##idx(void) \
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{ \
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@ -374,6 +683,7 @@ int spi_gd32_init(const struct device *dev)
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.clkid = DT_INST_CLOCKS_CELL(idx, id), \
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.reset = RESET_DT_SPEC_INST_GET(idx), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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IF_ENABLED(CONFIG_SPI_GD32_DMA, (.dma = DMAS_DECL(idx),)) \
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IF_ENABLED(CONFIG_SPI_GD32_INTERRUPT, \
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(.irq_configure = spi_gd32_irq_configure_##idx)) }; \
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DEVICE_DT_INST_DEFINE(idx, &spi_gd32_init, NULL, \
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|||
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Reference in a new issue