diff --git a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi new file mode 100644 index 00000000000..345f7654347 --- /dev/null +++ b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 EPAM Systems + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + compatible = "renesas,r9a08g045"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + clock-frequency = <250000000>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <7>; +}; diff --git a/modules/Kconfig.renesas_fsp b/modules/Kconfig.renesas_fsp index a13152f6da2..c3bc55f0016 100644 --- a/modules/Kconfig.renesas_fsp +++ b/modules/Kconfig.renesas_fsp @@ -8,6 +8,11 @@ config HAS_RENESAS_RA_FSP help Enable Renesas RA FSP support +config HAS_RENESAS_RZ_FSP + bool + help + Enable Renesas RZ FSP support + if HAS_RENESAS_RA_FSP config USE_RA_FSP_SCI_B_UART diff --git a/soc/renesas/rz/CMakeLists.txt b/soc/renesas/rz/CMakeLists.txt new file mode 100644 index 00000000000..52e7fc68a37 --- /dev/null +++ b/soc/renesas/rz/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/renesas/rz/Kconfig b/soc/renesas/rz/Kconfig new file mode 100644 index 00000000000..0987cc809c3 --- /dev/null +++ b/soc/renesas/rz/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RZ + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RENESAS_RZ diff --git a/soc/renesas/rz/Kconfig.defconfig b/soc/renesas/rz/Kconfig.defconfig new file mode 100644 index 00000000000..460b3387e76 --- /dev/null +++ b/soc/renesas/rz/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RZ + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_RENESAS_RZ diff --git a/soc/renesas/rz/Kconfig.soc b/soc/renesas/rz/Kconfig.soc new file mode 100644 index 00000000000..c6457e22521 --- /dev/null +++ b/soc/renesas/rz/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_RZ + bool + +config SOC_FAMILY + default "renesas_rz" if SOC_FAMILY_RENESAS_RZ + +rsource "*/Kconfig.soc" diff --git a/soc/renesas/rz/rzg3s/CMakeLists.txt b/soc/renesas/rz/rzg3s/CMakeLists.txt new file mode 100644 index 00000000000..2db47f0bb79 --- /dev/null +++ b/soc/renesas/rz/rzg3s/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rz/rzg3s/Kconfig b/soc/renesas/rz/rzg3s/Kconfig new file mode 100644 index 00000000000..15eaa95f178 --- /dev/null +++ b/soc/renesas/rz/rzg3s/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2024 EPAM Systems +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZG3S + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RZ_FSP + select CPU_CORTEX_M_HAS_DWT + select SOC_EARLY_INIT_HOOK diff --git a/soc/renesas/rz/rzg3s/Kconfig.defconfig b/soc/renesas/rz/rzg3s/Kconfig.defconfig new file mode 100644 index 00000000000..77439d92b82 --- /dev/null +++ b/soc/renesas/rz/rzg3s/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2024 EPAM Systems +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RZG3S + +config NUM_IRQS + default 480 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config SYS_CLOCK_EXISTS + default y + +# This is required to support debug with xSPI boot when Zephyr already booted by TF-A +config INIT_ARCH_HW_AT_BOOT + default y + +config BUILD_OUTPUT_S19 + default y + +endif # SOC_SERIES_RZG3S diff --git a/soc/renesas/rz/rzg3s/Kconfig.soc b/soc/renesas/rz/rzg3s/Kconfig.soc new file mode 100644 index 00000000000..dc65a2303ed --- /dev/null +++ b/soc/renesas/rz/rzg3s/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZG3S + bool + select SOC_FAMILY_RENESAS_RZ + help + Renesas RZ/G3S series + +config SOC_SERIES + default "rzg3s" if SOC_SERIES_RZG3S + +config SOC_R9A08G045S33GBG + bool + select SOC_SERIES_RZG3S + help + R9A08G045S33GBG + +config SOC_R9A08G045S33GBG_CM33 + bool + select SOC_R9A08G045S33GBG + +config SOC + default "r9a08g045s33gbg" if SOC_R9A08G045S33GBG diff --git a/soc/renesas/rz/rzg3s/soc.c b/soc/renesas/rz/rzg3s/soc.c new file mode 100644 index 00000000000..a263b91b283 --- /dev/null +++ b/soc/renesas/rz/rzg3s/soc.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RZ/G3S Group + */ + +#include +#include + +/* System core clock is set to 250 MHz by IPL of A55 */ +uint32_t SystemCoreClock = 250000000; + +void soc_early_init_hook(void) +{ + bsp_clock_init(); + + /* This delay is required to wait for the A55 to complete its setting first before */ + /* UART initialization of M33 */ + R_BSP_SoftwareDelay(CONFIG_UART_RENESAS_RZG_INIT_DELAY_MS, BSP_DELAY_UNITS_MILLISECONDS); +} diff --git a/soc/renesas/rz/rzg3s/soc.h b/soc/renesas/rz/rzg3s/soc.h new file mode 100644 index 00000000000..1d2a2d05cfd --- /dev/null +++ b/soc/renesas/rz/rzg3s/soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ */ diff --git a/soc/renesas/rz/soc.yml b/soc/renesas/rz/soc.yml new file mode 100644 index 00000000000..3cc8edd8baf --- /dev/null +++ b/soc/renesas/rz/soc.yml @@ -0,0 +1,8 @@ +family: + - name: renesas_rz + series: + - name: rzg3s + socs: + - name: r9a08g045s33gbg + cpuclusters: + - name: cm33